A DC-to-18 GHz 6-bit CMOS Digital Step Attenuator with Low Phase Error and Compact Size

Jianbin Liu; Tao Yang; Pei Ling Chi

doi:10.1109/ISEMC58300.2023.10370127

A DC-to-18 GHz 6-bit CMOS Digital Step Attenuator with Low Phase Error and Compact Size

Jianbin Liu, Tao Yang, Pei Ling Chi

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

Abstract

In this paper, a DC-to-18 GHz low phase error 6-bit digitally controlled attenuator fabricated in CMOS 55nm process is proposed. The proposed attenuator utilizes a phase-compensated structure to minimize the phase difference between the reference state and the attenuation state, resulting in a low root mean square (RMS) phase error. Additionally, the cascading method of the attenuation units is optimized to ensure accurate attenuation across a wide range. Experimental measurements demonstrate that the designed digital attenuator achieves a maximum RMS phase error of less than 4° within the operating frequency band. It offers an attenuation range of 31.5 dB with a step size of 0.5 dB. Remarkably, the core area, excluding the pad, occupies a small area of 0.015

Original language	English
Title of host publication	7th International Symposium on Electromagnetic Compatibility, ISEMC 2023 - Proceedings
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)	9798350333107
DOIs	https://doi.org/10.1109/ISEMC58300.2023.10370127
State	Published - 2023
Event	7th IEEE International Symposium on Electromagnetic Compatibility, ISEMC 2023 - Hangzhou, China Duration: 20 Oct 2023 → 23 Oct 2023

Publication series

Name	IEEE International Symposium on Electromagnetic Compatibility
ISSN (Print)	1077-4076
ISSN (Electronic)	2158-1118

Conference

Conference	7th IEEE International Symposium on Electromagnetic Compatibility, ISEMC 2023
Country/Territory	China
City	Hangzhou
Period	20/10/23 → 23/10/23

Keywords

CMOS
digital step attenuator
phase compensated structure
ultra-wide band (UWB)

Access to Document

10.1109/ISEMC58300.2023.10370127

Cite this

Liu, J., Yang, T., & Chi, P. L. (2023). A DC-to-18 GHz 6-bit CMOS Digital Step Attenuator with Low Phase Error and Compact Size. In 7th International Symposium on Electromagnetic Compatibility, ISEMC 2023 - Proceedings (IEEE International Symposium on Electromagnetic Compatibility). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ISEMC58300.2023.10370127

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title = "A DC-to-18 GHz 6-bit CMOS Digital Step Attenuator with Low Phase Error and Compact Size",

abstract = "In this paper, a DC-to-18 GHz low phase error 6-bit digitally controlled attenuator fabricated in CMOS 55nm process is proposed. The proposed attenuator utilizes a phase-compensated structure to minimize the phase difference between the reference state and the attenuation state, resulting in a low root mean square (RMS) phase error. Additionally, the cascading method of the attenuation units is optimized to ensure accurate attenuation across a wide range. Experimental measurements demonstrate that the designed digital attenuator achieves a maximum RMS phase error of less than 4° within the operating frequency band. It offers an attenuation range of 31.5 dB with a step size of 0.5 dB. Remarkably, the core area, excluding the pad, occupies a small area of 0.015",

keywords = "CMOS, digital step attenuator, phase compensated structure, ultra-wide band (UWB)",

author = "Jianbin Liu and Tao Yang and Chi, {Pei Ling}",

note = "Publisher Copyright: {\textcopyright} 2023 IEEE.; 7th IEEE International Symposium on Electromagnetic Compatibility, ISEMC 2023 ; Conference date: 20-10-2023 Through 23-10-2023",

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doi = "10.1109/ISEMC58300.2023.10370127",

language = "English",

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Liu, J, Yang, T & Chi, PL 2023, A DC-to-18 GHz 6-bit CMOS Digital Step Attenuator with Low Phase Error and Compact Size. in 7th International Symposium on Electromagnetic Compatibility, ISEMC 2023 - Proceedings. IEEE International Symposium on Electromagnetic Compatibility, Institute of Electrical and Electronics Engineers Inc., 7th IEEE International Symposium on Electromagnetic Compatibility, ISEMC 2023, Hangzhou, China, 20/10/23. https://doi.org/10.1109/ISEMC58300.2023.10370127

A DC-to-18 GHz 6-bit CMOS Digital Step Attenuator with Low Phase Error and Compact Size. / Liu, Jianbin; Yang, Tao; Chi, Pei Ling.
7th International Symposium on Electromagnetic Compatibility, ISEMC 2023 - Proceedings. Institute of Electrical and Electronics Engineers Inc., 2023. (IEEE International Symposium on Electromagnetic Compatibility).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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N2 - In this paper, a DC-to-18 GHz low phase error 6-bit digitally controlled attenuator fabricated in CMOS 55nm process is proposed. The proposed attenuator utilizes a phase-compensated structure to minimize the phase difference between the reference state and the attenuation state, resulting in a low root mean square (RMS) phase error. Additionally, the cascading method of the attenuation units is optimized to ensure accurate attenuation across a wide range. Experimental measurements demonstrate that the designed digital attenuator achieves a maximum RMS phase error of less than 4° within the operating frequency band. It offers an attenuation range of 31.5 dB with a step size of 0.5 dB. Remarkably, the core area, excluding the pad, occupies a small area of 0.015

AB - In this paper, a DC-to-18 GHz low phase error 6-bit digitally controlled attenuator fabricated in CMOS 55nm process is proposed. The proposed attenuator utilizes a phase-compensated structure to minimize the phase difference between the reference state and the attenuation state, resulting in a low root mean square (RMS) phase error. Additionally, the cascading method of the attenuation units is optimized to ensure accurate attenuation across a wide range. Experimental measurements demonstrate that the designed digital attenuator achieves a maximum RMS phase error of less than 4° within the operating frequency band. It offers an attenuation range of 31.5 dB with a step size of 0.5 dB. Remarkably, the core area, excluding the pad, occupies a small area of 0.015

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A DC-to-18 GHz 6-bit CMOS Digital Step Attenuator with Low Phase Error and Compact Size

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