A cost-effective reconfigurable accelerator for platform-based SoC design

Lan-Da Van; Hsin Fu Luo; Nien Hsiang Chang; Chun Ming Huang

doi:10.1109/ISCAS.2006.1693000

A cost-effective reconfigurable accelerator for platform-based SoC design

Lan-Da Van^*, Hsin Fu Luo, Nien Hsiang Chang, Chun Ming Huang

^*Corresponding author for this work

Department of Computer Science

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

Abstract

In this paper, we propose a cost-effective reconfigurable accelerator for the platform-based system-on-a-chip (SoC) design. Based on the proposed design methodology, the reconfigurable computation array (RCA) can be landed with the features of high usage rate and low hardware cost without sacrificing multimedia computation performance. The RCA consisting of 8 type 1 grouped processing elements (GPE1's), 3 GPE2's and 1 GPE3 is capable of configuring two 16×16-bit multiplication, eight 8×8 multiplication, and sixteen 8-bit absolute operations in different connection topologies. Via the cost-effective RCA, the number of GPEs can be saved up to 25% and the usage rates of the RCA compared with that of [8] for motion estimation (ME), RGB2YUV and DCT/IDCT can be improved by 25%, 18.7%, and 23.9%, respectively.

Original language	English
Title of host publication	ISCAS 2006
Subtitle of host publication	2006 IEEE International Symposium on Circuits and Systems, Proceedings
Pages	1977-1980
Number of pages	4
DOIs	https://doi.org/10.1109/ISCAS.2006.1693000
State	Published - 1 Dec 2006
Event	ISCAS 2006: 2006 IEEE International Symposium on Circuits and Systems - Kos, Greece Duration: 21 May 2006 → 24 May 2006

Publication series

Name	Proceedings - IEEE International Symposium on Circuits and Systems
ISSN (Print)	0271-4310

Conference

Conference	ISCAS 2006: 2006 IEEE International Symposium on Circuits and Systems
Country/Territory	Greece
City	Kos
Period	21/05/06 → 24/05/06

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10.1109/ISCAS.2006.1693000

Cite this

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title = "A cost-effective reconfigurable accelerator for platform-based SoC design",

abstract = "In this paper, we propose a cost-effective reconfigurable accelerator for the platform-based system-on-a-chip (SoC) design. Based on the proposed design methodology, the reconfigurable computation array (RCA) can be landed with the features of high usage rate and low hardware cost without sacrificing multimedia computation performance. The RCA consisting of 8 type 1 grouped processing elements (GPE1's), 3 GPE2's and 1 GPE3 is capable of configuring two 16×16-bit multiplication, eight 8×8 multiplication, and sixteen 8-bit absolute operations in different connection topologies. Via the cost-effective RCA, the number of GPEs can be saved up to 25% and the usage rates of the RCA compared with that of [8] for motion estimation (ME), RGB2YUV and DCT/IDCT can be improved by 25%, 18.7%, and 23.9%, respectively.",

author = "Lan-Da Van and Luo, {Hsin Fu} and Chang, {Nien Hsiang} and Huang, {Chun Ming}",

year = "2006",

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doi = "10.1109/ISCAS.2006.1693000",

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series = "Proceedings - IEEE International Symposium on Circuits and Systems",

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}

Van, L-D, Luo, HF, Chang, NH & Huang, CM 2006, A cost-effective reconfigurable accelerator for platform-based SoC design. in ISCAS 2006: 2006 IEEE International Symposium on Circuits and Systems, Proceedings., 1693000, Proceedings - IEEE International Symposium on Circuits and Systems, pp. 1977-1980, ISCAS 2006: 2006 IEEE International Symposium on Circuits and Systems, Kos, Greece, 21/05/06. https://doi.org/10.1109/ISCAS.2006.1693000

A cost-effective reconfigurable accelerator for platform-based SoC design. / Van, Lan-Da; Luo, Hsin Fu; Chang, Nien Hsiang et al.
ISCAS 2006: 2006 IEEE International Symposium on Circuits and Systems, Proceedings. 2006. p. 1977-1980 1693000 (Proceedings - IEEE International Symposium on Circuits and Systems).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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AB - In this paper, we propose a cost-effective reconfigurable accelerator for the platform-based system-on-a-chip (SoC) design. Based on the proposed design methodology, the reconfigurable computation array (RCA) can be landed with the features of high usage rate and low hardware cost without sacrificing multimedia computation performance. The RCA consisting of 8 type 1 grouped processing elements (GPE1's), 3 GPE2's and 1 GPE3 is capable of configuring two 16×16-bit multiplication, eight 8×8 multiplication, and sixteen 8-bit absolute operations in different connection topologies. Via the cost-effective RCA, the number of GPEs can be saved up to 25% and the usage rates of the RCA compared with that of [8] for motion estimation (ME), RGB2YUV and DCT/IDCT can be improved by 25%, 18.7%, and 23.9%, respectively.

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A cost-effective reconfigurable accelerator for platform-based SoC design

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