A cost effective BIST second-order Σ-Δ modulator

Hao-Chiao Hong; Sheng Chuan Liang; Hong Chin Song

doi:10.1109/DDECS.2008.4538809

A cost effective BIST second-order Σ-Δ modulator

Hao-Chiao Hong^*, Sheng Chuan Liang, Hong Chin Song

^*Corresponding author for this work

Department of Electrical and Computer Engineering

Research output: Contribution to conference › Paper › peer-review

6 Scopus citations

Abstract

This paper demonstrates a cost effective built-in-self-test (BIST) Σ-Δ modulator prototype. The BIST prototype is composed of a design-for-digital-testability second-order Σ-Δ modulator chip and a FPGA which implements the digital BIST functions. The BIST system is based on the modified control sine wave fitting (MCSWF) procedure. Different from the conventional analysis method using Fast Fourier Transform (FFT), this implementation requires neither any parallel multiplier nor complex CPU/DSP and bulky memory. Measurement results show that the BIST prototype gives a signal-to-noise-and-distortion ratio (SNDR) result of 74.3 dB which is within 0.3 dB comparing with the FFT counterpart. The proposed BIST implementation achieves the advantages of compact hardware, high accuracy, and the flexibility of adjusting the stimuli which are important features for BIST applications.

Original language	English
Pages	314-319
Number of pages	6
DOIs	https://doi.org/10.1109/DDECS.2008.4538809
State	Published - 2008
Event	2008 IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems, DDECS - Bratislava, Slovakia Duration: 16 Apr 2008 → 18 Apr 2008

Conference

Conference	2008 IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems, DDECS
Country/Territory	Slovakia
City	Bratislava
Period	16/04/08 → 18/04/08

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10.1109/DDECS.2008.4538809

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@conference{3d1a1527b67648ea834e2764c4a8cbf2,

title = "A cost effective BIST second-order Σ-Δ modulator",

abstract = "This paper demonstrates a cost effective built-in-self-test (BIST) Σ-Δ modulator prototype. The BIST prototype is composed of a design-for-digital-testability second-order Σ-Δ modulator chip and a FPGA which implements the digital BIST functions. The BIST system is based on the modified control sine wave fitting (MCSWF) procedure. Different from the conventional analysis method using Fast Fourier Transform (FFT), this implementation requires neither any parallel multiplier nor complex CPU/DSP and bulky memory. Measurement results show that the BIST prototype gives a signal-to-noise-and-distortion ratio (SNDR) result of 74.3 dB which is within 0.3 dB comparing with the FFT counterpart. The proposed BIST implementation achieves the advantages of compact hardware, high accuracy, and the flexibility of adjusting the stimuli which are important features for BIST applications.",

author = "Hao-Chiao Hong and Liang, {Sheng Chuan} and Song, {Hong Chin}",

year = "2008",

doi = "10.1109/DDECS.2008.4538809",

language = "English",

pages = "314--319",

note = "2008 IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems, DDECS ; Conference date: 16-04-2008 Through 18-04-2008",

}

TY - CONF

T1 - A cost effective BIST second-order Σ-Δ modulator

AU - Hong, Hao-Chiao

AU - Liang, Sheng Chuan

AU - Song, Hong Chin

PY - 2008

Y1 - 2008

N2 - This paper demonstrates a cost effective built-in-self-test (BIST) Σ-Δ modulator prototype. The BIST prototype is composed of a design-for-digital-testability second-order Σ-Δ modulator chip and a FPGA which implements the digital BIST functions. The BIST system is based on the modified control sine wave fitting (MCSWF) procedure. Different from the conventional analysis method using Fast Fourier Transform (FFT), this implementation requires neither any parallel multiplier nor complex CPU/DSP and bulky memory. Measurement results show that the BIST prototype gives a signal-to-noise-and-distortion ratio (SNDR) result of 74.3 dB which is within 0.3 dB comparing with the FFT counterpart. The proposed BIST implementation achieves the advantages of compact hardware, high accuracy, and the flexibility of adjusting the stimuli which are important features for BIST applications.

AB - This paper demonstrates a cost effective built-in-self-test (BIST) Σ-Δ modulator prototype. The BIST prototype is composed of a design-for-digital-testability second-order Σ-Δ modulator chip and a FPGA which implements the digital BIST functions. The BIST system is based on the modified control sine wave fitting (MCSWF) procedure. Different from the conventional analysis method using Fast Fourier Transform (FFT), this implementation requires neither any parallel multiplier nor complex CPU/DSP and bulky memory. Measurement results show that the BIST prototype gives a signal-to-noise-and-distortion ratio (SNDR) result of 74.3 dB which is within 0.3 dB comparing with the FFT counterpart. The proposed BIST implementation achieves the advantages of compact hardware, high accuracy, and the flexibility of adjusting the stimuli which are important features for BIST applications.

UR - http://www.scopus.com/inward/record.url?scp=50649083501&partnerID=8YFLogxK

U2 - 10.1109/DDECS.2008.4538809

DO - 10.1109/DDECS.2008.4538809

M3 - Paper

AN - SCOPUS:50649083501

SP - 314

EP - 319

T2 - 2008 IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems, DDECS

Y2 - 16 April 2008 through 18 April 2008

ER -

A cost effective BIST second-order Σ-Δ modulator

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