A Controlled-Avalanche Superlattice Transistor

Pallab K. Bhattacharya, Albert Chin, Kwang S. Seo

Research output: Contribution to journalArticlepeer-review

2 Scopus citations


A novel bipolar avalanche transistor is proposed. Controlled avalanche and large current output over a significant bias region is achieved by incorporating a staircase multiplication region at the base-collector junction. The III-V materials choice, device design, and computed output characteristics are presented and discussed.

Original languageEnglish
Pages (from-to)19-21
Number of pages3
JournalIeee Electron Device Letters
Issue number1
StatePublished - Jan 1987


Dive into the research topics of 'A Controlled-Avalanche Superlattice Transistor'. Together they form a unique fingerprint.

Cite this