A Controlled-Avalanche Superlattice Transistor

Pallab K. Bhattacharya; Albert Chin; Kwang S. Seo

doi:10.1109/EDL.1987.26536

A Controlled-Avalanche Superlattice Transistor

Pallab K. Bhattacharya, Albert Chin, Kwang S. Seo

Institute of Electronics

Research output: Contribution to journal › Article › peer-review

2 Scopus citations

Abstract

A novel bipolar avalanche transistor is proposed. Controlled avalanche and large current output over a significant bias region is achieved by incorporating a staircase multiplication region at the base-collector junction. The III-V materials choice, device design, and computed output characteristics are presented and discussed.

Original language	English
Pages (from-to)	19-21
Number of pages	3
Journal	Ieee Electron Device Letters
Volume	8
Issue number	1
DOIs	https://doi.org/10.1109/EDL.1987.26536
State	Published - Jan 1987

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title = "A Controlled-Avalanche Superlattice Transistor",

abstract = "A novel bipolar avalanche transistor is proposed. Controlled avalanche and large current output over a significant bias region is achieved by incorporating a staircase multiplication region at the base-collector junction. The III-V materials choice, device design, and computed output characteristics are presented and discussed.",

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A Controlled-Avalanche Superlattice Transistor

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