A Controlled-Avalanche Superlattice Transistor

Pallab K. Bhattacharya, Albert Chin, Kwang S. Seo

Research output: Contribution to journalArticlepeer-review

2 Scopus citations

Abstract

A novel bipolar avalanche transistor is proposed. Controlled avalanche and large current output over a significant bias region is achieved by incorporating a staircase multiplication region at the base-collector junction. The III-V materials choice, device design, and computed output characteristics are presented and discussed.

Original languageEnglish
Pages (from-to)19-21
Number of pages3
JournalIEEE Electron Device Letters
Volume8
Issue number1
DOIs
StatePublished - 1 Jan 1987

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