Abstract
A novel bipolar avalanche transistor is proposed. Controlled avalanche and large current output over a significant bias region is achieved by incorporating a staircase multiplication region at the base-collector junction. The III-V materials choice, device design, and computed output characteristics are presented and discussed.
Original language | English |
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Pages (from-to) | 19-21 |
Number of pages | 3 |
Journal | Ieee Electron Device Letters |
Volume | 8 |
Issue number | 1 |
DOIs | |
State | Published - Jan 1987 |