A continuous-time delta-sigma modulator using feedback resistors

Yung Chou Lin*, Wen Hung Hsieh, Chung-Chih Hung

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

1 Scopus citations

Abstract

A third-order continuous-time delta-sigma comprised of Active- RC integrator and Gm-C integrator is presented. For the consideration of power, linearity and performance, the first integrator uses active-RC OpAmp and the others use Gm-C. To reduce the clock jitter sensitivity, we choose nonreturn-to-zero (NRZ) pulse shaping as our DAC type. For the realization of NTF zero optimization, we use resistors to reduce power consumption. The delta-sigma modulator is implemented in standard digital 0.18-μm CMOS process which achieves a 60-dB SNDR or 10-bits ENOB over a 1-MHz signal bandwidth at an OSR of 50. The power consumption of the continuous-time delta-sigma modulator itself is 13.7 mW from the 1.8-V supply.

Original languageEnglish
Title of host publication2009 International Symposium on VLSI Design, Automation and Test, VLSI-DAT '09
Pages243-246
Number of pages4
DOIs
StatePublished - 2009
Event2009 International Symposium on VLSI Design, Automation and Test, VLSI-DAT '09 - Hsinchu, Taiwan
Duration: 28 Apr 200930 Apr 2009

Publication series

Name2009 International Symposium on VLSI Design, Automation and Test, VLSI-DAT '09

Conference

Conference2009 International Symposium on VLSI Design, Automation and Test, VLSI-DAT '09
Country/TerritoryTaiwan
CityHsinchu
Period28/04/0930/04/09

Keywords

  • Continuous-time
  • Delta-sigma
  • Gm-C
  • Modulator

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