TY - GEN
T1 - A Compact 3T1F FeRAM Compute Cell for In-Memory MAC Using Partial Polarization Switching
AU - Singh, Vikrant
AU - Bulusu, Anand
AU - Pahwa, Girish
N1 - Publisher Copyright:
© 2026 IEEE.
PY - 2026
Y1 - 2026
N2 - In-memory computing (IMC) alleviates data-movement overhead in AI workloads by performing multiply-accumulate (MAC) operations inside memory arrays. Ferro-electric capacitors (FeCAPs) offer non-volatility and analog charge response, but conventional FeRAM readout is destructive. This work proposes a compact 3T1F FeRAM compute cell that uses partial polarization switching to enable quasi-non-destructive readout during MAC. A nucleation-limited-switching (NLS) FeCAP model captures pulse-width-dependent switching behavior. A pre-conditioning pulse establishes a stable ∼100 mV differential at the internal floating node for opposite polarization states, enabling multiple MAC cycles before weight refresh. A 4-bit weight is implemented using four 3T1F cells, and SPICE simulations on a 4 × 4 array confirm correct MAC operation and stable partial-switching readout.
AB - In-memory computing (IMC) alleviates data-movement overhead in AI workloads by performing multiply-accumulate (MAC) operations inside memory arrays. Ferro-electric capacitors (FeCAPs) offer non-volatility and analog charge response, but conventional FeRAM readout is destructive. This work proposes a compact 3T1F FeRAM compute cell that uses partial polarization switching to enable quasi-non-destructive readout during MAC. A nucleation-limited-switching (NLS) FeCAP model captures pulse-width-dependent switching behavior. A pre-conditioning pulse establishes a stable ∼100 mV differential at the internal floating node for opposite polarization states, enabling multiple MAC cycles before weight refresh. A 4-bit weight is implemented using four 3T1F cells, and SPICE simulations on a 4 × 4 array confirm correct MAC operation and stable partial-switching readout.
KW - FeRAM
KW - IMC
KW - MAC
KW - Non-destructive read
UR - https://www.scopus.com/pages/publications/105041809465
U2 - 10.1109/VLSITSA69131.2026.11527876
DO - 10.1109/VLSITSA69131.2026.11527876
M3 - Conference contribution
AN - SCOPUS:105041809465
T3 - 2026 International VLSI Symposium on Technology, Systems and Applications, VLSI TSA 2026 - Proceedings of Technical Papers
BT - 2026 International VLSI Symposium on Technology, Systems and Applications, VLSI TSA 2026 - Proceedings of Technical Papers
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 2026 International VLSI Symposium on Technology, Systems and Applications, VLSI TSA 2026
Y2 - 13 April 2026 through 17 April 2026
ER -