A CMOS-Process-Compatible Low-Voltage Junction-FET with Adjustable Pinch-Off Voltage

Karuna Nidhi*, Ming-Dou Ker

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

5 Scopus citations


A novel horizontal n-channel junction field-effect transistor (n-JFET) device is proposed and verified in a 0.25-μm bulk CMOS process. This horizontal JFET consists of alternating n- and p-regions formed by using the P-type electro-static discharge (ESD) implantation. P-type ESD implantation has been an optional and commonly well supported process step by most of foundries to improve ESD robustness of the I/O devices. Device parameters such as the pinch-off voltage (VP) and the zero-bias drain current (IDS0) of the proposed n-JFET device can be modified by adjusting the P+ separation (L) in the layout. With the adjustable pinch-off voltages, this device can be used for different circuit applications. The 2-D device simulations with technology computer aided design are used to analyze the depletion region and to verify the pinch-off voltage under different L values. The pinch-off voltage remains almost unchanged with the temperature variations. In addition, SPICE simulation results show good agreement with the experimental silicon (Si) data in term of ID-VD and ID-VG.

Original languageEnglish
Article number7937877
Pages (from-to)2812-2819
Number of pages8
JournalIEEE Transactions on Electron Devices
Issue number7
StatePublished - 1 Jul 2017


  • CMOS process
  • ESD implantation
  • junction field-effect transistor (JFET)
  • pinch-off voltage (V)
  • zero-bias drain current (I)


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