A CMOS-Process-Compatible Low-Voltage Junction-FET with Adjustable Pinch-Off Voltage

Karuna Nidhi; Ming-Dou Ker

doi:10.1109/TED.2017.2706423

A CMOS-Process-Compatible Low-Voltage Junction-FET with Adjustable Pinch-Off Voltage

Karuna Nidhi^*, Ming-Dou Ker

^*Corresponding author for this work

Institute of Electronics

Research output: Contribution to journal › Article › peer-review

5 Scopus citations

Abstract

A novel horizontal n-channel junction field-effect transistor (n-JFET) device is proposed and verified in a 0.25-μm bulk CMOS process. This horizontal JFET consists of alternating n- and p-regions formed by using the P-type electro-static discharge (ESD) implantation. P-type ESD implantation has been an optional and commonly well supported process step by most of foundries to improve ESD robustness of the I/O devices. Device parameters such as the pinch-off voltage (V_P) and the zero-bias drain current (I_DS0) of the proposed n-JFET device can be modified by adjusting the P+ separation (L) in the layout. With the adjustable pinch-off voltages, this device can be used for different circuit applications. The 2-D device simulations with technology computer aided design are used to analyze the depletion region and to verify the pinch-off voltage under different L values. The pinch-off voltage remains almost unchanged with the temperature variations. In addition, SPICE simulation results show good agreement with the experimental silicon (Si) data in term of I_D-V_D and I_D-V_G.

Original language	English
Article number	7937877
Pages (from-to)	2812-2819
Number of pages	8
Journal	IEEE Transactions on Electron Devices
Volume	64
Issue number	7
DOIs	https://doi.org/10.1109/TED.2017.2706423
State	Published - 1 Jul 2017

Keywords

CMOS process
ESD implantation
SPICE
junction field-effect transistor (JFET)
pinch-off voltage (V)
zero-bias drain current (I)

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10.1109/TED.2017.2706423

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title = "A CMOS-Process-Compatible Low-Voltage Junction-FET with Adjustable Pinch-Off Voltage",

abstract = "A novel horizontal n-channel junction field-effect transistor (n-JFET) device is proposed and verified in a 0.25-μm bulk CMOS process. This horizontal JFET consists of alternating n- and p-regions formed by using the P-type electro-static discharge (ESD) implantation. P-type ESD implantation has been an optional and commonly well supported process step by most of foundries to improve ESD robustness of the I/O devices. Device parameters such as the pinch-off voltage (VP) and the zero-bias drain current (IDS0) of the proposed n-JFET device can be modified by adjusting the P+ separation (L) in the layout. With the adjustable pinch-off voltages, this device can be used for different circuit applications. The 2-D device simulations with technology computer aided design are used to analyze the depletion region and to verify the pinch-off voltage under different L values. The pinch-off voltage remains almost unchanged with the temperature variations. In addition, SPICE simulation results show good agreement with the experimental silicon (Si) data in term of ID-VD and ID-VG.",

keywords = "CMOS process, ESD implantation, SPICE, junction field-effect transistor (JFET), pinch-off voltage (V), zero-bias drain current (I)",

author = "Karuna Nidhi and Ming-Dou Ker",

year = "2017",

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doi = "10.1109/TED.2017.2706423",

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T1 - A CMOS-Process-Compatible Low-Voltage Junction-FET with Adjustable Pinch-Off Voltage

AU - Nidhi, Karuna

AU - Ker, Ming-Dou

PY - 2017/7/1

Y1 - 2017/7/1

N2 - A novel horizontal n-channel junction field-effect transistor (n-JFET) device is proposed and verified in a 0.25-μm bulk CMOS process. This horizontal JFET consists of alternating n- and p-regions formed by using the P-type electro-static discharge (ESD) implantation. P-type ESD implantation has been an optional and commonly well supported process step by most of foundries to improve ESD robustness of the I/O devices. Device parameters such as the pinch-off voltage (VP) and the zero-bias drain current (IDS0) of the proposed n-JFET device can be modified by adjusting the P+ separation (L) in the layout. With the adjustable pinch-off voltages, this device can be used for different circuit applications. The 2-D device simulations with technology computer aided design are used to analyze the depletion region and to verify the pinch-off voltage under different L values. The pinch-off voltage remains almost unchanged with the temperature variations. In addition, SPICE simulation results show good agreement with the experimental silicon (Si) data in term of ID-VD and ID-VG.

AB - A novel horizontal n-channel junction field-effect transistor (n-JFET) device is proposed and verified in a 0.25-μm bulk CMOS process. This horizontal JFET consists of alternating n- and p-regions formed by using the P-type electro-static discharge (ESD) implantation. P-type ESD implantation has been an optional and commonly well supported process step by most of foundries to improve ESD robustness of the I/O devices. Device parameters such as the pinch-off voltage (VP) and the zero-bias drain current (IDS0) of the proposed n-JFET device can be modified by adjusting the P+ separation (L) in the layout. With the adjustable pinch-off voltages, this device can be used for different circuit applications. The 2-D device simulations with technology computer aided design are used to analyze the depletion region and to verify the pinch-off voltage under different L values. The pinch-off voltage remains almost unchanged with the temperature variations. In addition, SPICE simulation results show good agreement with the experimental silicon (Si) data in term of ID-VD and ID-VG.

KW - CMOS process

KW - ESD implantation

KW - SPICE

KW - junction field-effect transistor (JFET)

KW - pinch-off voltage (V)

KW - zero-bias drain current (I)

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ER -

A CMOS-Process-Compatible Low-Voltage Junction-FET with Adjustable Pinch-Off Voltage

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Keywords

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