A CMOS Buffer Amplifier with Slew-Rate Enhancement and Power Saving Techniques

Liang Jie Lu, Po Hsun Chu, Wei Chen Huang, Yu Te Liao

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

This paper presents a low-power buffer amplifier with a high slew rate. The buffer amplifier with cross-coupled input pairs and positive feedback enhances the driving current at the transients dynamically. The adaptive bias-switching scheme reduces static power consumption. The design was fabricated in a 0.18-μ m CMOS process. The proposed amplifier offers a slew rate of 13.42 V/μ s at a load capacitor of 100 pF with a static current of 2.38 μ A, which is 80 times better than the one without the current-boosting scheme. The chip area is 189× 144 μ m2.

Original languageEnglish
Title of host publication2023 International VLSI Symposium on Technology, Systems and Applications, VLSI-TSA/VLSI-DAT 2023 - Proceedings
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9798350334166
DOIs
StatePublished - 2023
Event2023 International VLSI Symposium on Technology, Systems and Applications, VLSI-TSA/VLSI-DAT 2023 - Hsinchu, Taiwan
Duration: 17 Apr 202320 Apr 2023

Publication series

Name2023 International VLSI Symposium on Technology, Systems and Applications, VLSI-TSA/VLSI-DAT 2023 - Proceedings

Conference

Conference2023 International VLSI Symposium on Technology, Systems and Applications, VLSI-TSA/VLSI-DAT 2023
Country/TerritoryTaiwan
CityHsinchu
Period17/04/2320/04/23

Keywords

  • CMOS
  • driver
  • power-efficient
  • slew rate

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