A cache aware multithreading decision scheme on GPGPUs

Ta Kang Yen, Bo Yao Yu, Bo-Cheng Lai

    Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

    Abstract

    GPGPUs have emerged as one of the most widely used throughput processors. Deep multithreading and on-chip cache hierarchy are the two effective designs to achieve high throughput computing in modern GPGPUs. However, excessive multithreading could aggravate the cache contention while conservative multithreading could leave the execution resource under-utilized. Finding a proper design point between the two has become a significant performance factor to GPGPUs. This paper investigates the correlation between caching behavior and multithreading technique. By demonstrating the trade-off issue between the multithreading and cache contention, this paper proposes a multithreading decision scheme to dynamically adjusts the multithreading degree to achieve superior performance. With the proposed decision scheme, the system performance of memory-intensive workloads can be improved by 60% in average.

    Original languageEnglish
    Title of host publicationProceedings - 2014 IEEE 8th International Symposium on Embedded Multicore/Manycore SoCs, MCSoC 2014
    PublisherInstitute of Electrical and Electronics Engineers Inc.
    Pages267-272
    Number of pages6
    ISBN (Electronic)9781479943050
    DOIs
    StatePublished - 6 Nov 2014
    Event2014 8th IEEE International Symposium on Embedded Multicore/Manycore SoCs, MCSoC 2014 - Aizu-Wakamatsu, Japan
    Duration: 23 Sep 201425 Sep 2014

    Publication series

    NameProceedings - 2014 IEEE 8th International Symposium on Embedded Multicore/Manycore SoCs, MCSoC 2014

    Conference

    Conference2014 8th IEEE International Symposium on Embedded Multicore/Manycore SoCs, MCSoC 2014
    Country/TerritoryJapan
    CityAizu-Wakamatsu
    Period23/09/1425/09/14

    Keywords

    • design and optimization
    • GPGPU
    • Memory performance
    • multithreading

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