A bending n-well ballast layout to improve esd robustness in fully-silicided CMOS technology

Yong Ru Wen; Ming-Dou Ker; Wen Yi Chen

doi:10.1109/IRPS.2010.5488718

A bending n-well ballast layout to improve esd robustness in fully-silicided CMOS technology

Yong Ru Wen^*, Ming-Dou Ker, Wen Yi Chen

^*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

3 Scopus citations

Abstract

Ballast technique has been reported as a cost effective method to improve ESD robustness of fully-silicided devices without using silicide block. In this work, a new ballast technique, the bending N-Well (BNW) ballast structure, is proposed to enhance ESD robustness of fully-silicided NMOS. With a deep N-Well to cover the fully-silicided NMOS with BNW ballast structure, ESD robustness of the NMOS can be further improved by enhancing the turn-on uniformity among the multi-fingers of the NMOS.

Original language	English
Title of host publication	2010 IEEE International Reliability Physics Symposium, IRPS 2010
Pages	857-860
Number of pages	4
DOIs	https://doi.org/10.1109/IRPS.2010.5488718
State	Published - 20 Oct 2010
Event	2010 IEEE International Reliability Physics Symposium, IRPS 2010 - Garden Grove, CA, Canada Duration: 2 May 2010 → 6 May 2010

Publication series

Name	IEEE International Reliability Physics Symposium Proceedings
ISSN (Print)	1541-7026

Conference

Conference	2010 IEEE International Reliability Physics Symposium, IRPS 2010
Country/Territory	Canada
City	Garden Grove, CA
Period	2/05/10 → 6/05/10

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10.1109/IRPS.2010.5488718

Cite this

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title = "A bending n-well ballast layout to improve esd robustness in fully-silicided CMOS technology",

abstract = "Ballast technique has been reported as a cost effective method to improve ESD robustness of fully-silicided devices without using silicide block. In this work, a new ballast technique, the bending N-Well (BNW) ballast structure, is proposed to enhance ESD robustness of fully-silicided NMOS. With a deep N-Well to cover the fully-silicided NMOS with BNW ballast structure, ESD robustness of the NMOS can be further improved by enhancing the turn-on uniformity among the multi-fingers of the NMOS.",

author = "Wen, {Yong Ru} and Ming-Dou Ker and Chen, {Wen Yi}",

year = "2010",

month = oct,

day = "20",

doi = "10.1109/IRPS.2010.5488718",

language = "English",

isbn = "9781424454310",

series = "IEEE International Reliability Physics Symposium Proceedings",

pages = "857--860",

booktitle = "2010 IEEE International Reliability Physics Symposium, IRPS 2010",

note = "2010 IEEE International Reliability Physics Symposium, IRPS 2010 ; Conference date: 02-05-2010 Through 06-05-2010",

}

Wen, YR, Ker, M-D & Chen, WY 2010, A bending n-well ballast layout to improve esd robustness in fully-silicided CMOS technology. in 2010 IEEE International Reliability Physics Symposium, IRPS 2010., 5488718, IEEE International Reliability Physics Symposium Proceedings, pp. 857-860, 2010 IEEE International Reliability Physics Symposium, IRPS 2010, Garden Grove, CA, Canada, 2/05/10. https://doi.org/10.1109/IRPS.2010.5488718

A bending n-well ballast layout to improve esd robustness in fully-silicided CMOS technology. / Wen, Yong Ru; Ker, Ming-Dou; Chen, Wen Yi.
2010 IEEE International Reliability Physics Symposium, IRPS 2010. 2010. p. 857-860 5488718 (IEEE International Reliability Physics Symposium Proceedings).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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Y1 - 2010/10/20

N2 - Ballast technique has been reported as a cost effective method to improve ESD robustness of fully-silicided devices without using silicide block. In this work, a new ballast technique, the bending N-Well (BNW) ballast structure, is proposed to enhance ESD robustness of fully-silicided NMOS. With a deep N-Well to cover the fully-silicided NMOS with BNW ballast structure, ESD robustness of the NMOS can be further improved by enhancing the turn-on uniformity among the multi-fingers of the NMOS.

AB - Ballast technique has been reported as a cost effective method to improve ESD robustness of fully-silicided devices without using silicide block. In this work, a new ballast technique, the bending N-Well (BNW) ballast structure, is proposed to enhance ESD robustness of fully-silicided NMOS. With a deep N-Well to cover the fully-silicided NMOS with BNW ballast structure, ESD robustness of the NMOS can be further improved by enhancing the turn-on uniformity among the multi-fingers of the NMOS.

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M3 - Conference contribution

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SN - 9781424454310

T3 - IEEE International Reliability Physics Symposium Proceedings

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BT - 2010 IEEE International Reliability Physics Symposium, IRPS 2010

T2 - 2010 IEEE International Reliability Physics Symposium, IRPS 2010

Y2 - 2 May 2010 through 6 May 2010

ER -

A bending n-well ballast layout to improve esd robustness in fully-silicided CMOS technology

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