A 94.3% Peak Efficiency Adaptive Switchable CCM and DCM Single-Inductor Multiple-Output Converter with 0.03 mV/mA Low Crosstalk and 185 nA Ultralow Quiescent

Tzu Hsien Yang; Yong Hwa Wen; Yu Jheng Ouyang; Chun Kai Chiu; Bo Kuan Wu; Ke Horng Chen; Ying Hsi Lin; Shian Ru Lin; Tsung Yen Tsai

doi:10.1109/JSSC.2022.3142207

A 94.3% Peak Efficiency Adaptive Switchable CCM and DCM Single-Inductor Multiple-Output Converter with 0.03 mV/mA Low Crosstalk and 185 nA Ultralow Quiescent

Tzu Hsien Yang, Yong Hwa Wen, Yu Jheng Ouyang, Chun Kai Chiu, Bo Kuan Wu, Ke Horng Chen^*, Ying Hsi Lin, Shian Ru Lin, Tsung Yen Tsai

^*Corresponding author for this work

Department of Electrical and Computer Engineering

Research output: Contribution to journal › Article › peer-review

12 Scopus citations

Abstract

This article proposes a single-inductor multi-output converter implemented in 0.153 \mu{\mathrm {m}} CMOS process, including the adaptive switchable continuous conduction mode (CCM) and discontinuous conduction mode (DCM) (ASCD) technique, and a five-input crosstalk reduction error amplifier (CREA) to minimize the cross regulation to 0.03 mV/mA and achieve load capability up to 3 W. At ultra-light loads, the proposed ultralow power (ULP) mode is applied to reach 185 nA quiescent current and enhance light load power efficiency. Moreover, the peak efficiency is as high as 94.3% with a chip area of 1.2 \times 1.7 mm2.

Original language	English
Pages (from-to)	2731-2740
Number of pages	10
Journal	IEEE Journal of Solid-State Circuits
Volume	57
Issue number	9
DOIs	https://doi.org/10.1109/JSSC.2022.3142207
State	Published - 1 Sep 2022

Keywords

Continuous conduction mode (CCM)
cross regulation
discontinuous conduction mode (DCM)
single-inductor multi-output (SIMO)
ultralow quiescent current

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Yang, T. H., Wen, Y. H., Ouyang, Y. J., Chiu, C. K., Wu, B. K., Chen, K. H., Lin, Y. H., Lin, S. R., & Tsai, T. Y. (2022). A 94.3% Peak Efficiency Adaptive Switchable CCM and DCM Single-Inductor Multiple-Output Converter with 0.03 mV/mA Low Crosstalk and 185 nA Ultralow Quiescent. IEEE Journal of Solid-State Circuits, 57(9), 2731-2740. https://doi.org/10.1109/JSSC.2022.3142207

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abstract = "This article proposes a single-inductor multi-output converter implemented in 0.153 \mu{\mathrm {m}} CMOS process, including the adaptive switchable continuous conduction mode (CCM) and discontinuous conduction mode (DCM) (ASCD) technique, and a five-input crosstalk reduction error amplifier (CREA) to minimize the cross regulation to 0.03 mV/mA and achieve load capability up to 3 W. At ultra-light loads, the proposed ultralow power (ULP) mode is applied to reach 185 nA quiescent current and enhance light load power efficiency. Moreover, the peak efficiency is as high as 94.3% with a chip area of 1.2 \times 1.7 mm2.",

keywords = "Continuous conduction mode (CCM), cross regulation, discontinuous conduction mode (DCM), single-inductor multi-output (SIMO), ultralow quiescent current",

author = "Yang, {Tzu Hsien} and Wen, {Yong Hwa} and Ouyang, {Yu Jheng} and Chiu, {Chun Kai} and Wu, {Bo Kuan} and Chen, {Ke Horng} and Lin, {Ying Hsi} and Lin, {Shian Ru} and Tsai, {Tsung Yen}",

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AU - Yang, Tzu Hsien

AU - Wen, Yong Hwa

AU - Ouyang, Yu Jheng

AU - Chiu, Chun Kai

AU - Wu, Bo Kuan

AU - Chen, Ke Horng

AU - Lin, Ying Hsi

AU - Lin, Shian Ru

AU - Tsai, Tsung Yen

PY - 2022/9/1

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N2 - This article proposes a single-inductor multi-output converter implemented in 0.153 \mu{\mathrm {m}} CMOS process, including the adaptive switchable continuous conduction mode (CCM) and discontinuous conduction mode (DCM) (ASCD) technique, and a five-input crosstalk reduction error amplifier (CREA) to minimize the cross regulation to 0.03 mV/mA and achieve load capability up to 3 W. At ultra-light loads, the proposed ultralow power (ULP) mode is applied to reach 185 nA quiescent current and enhance light load power efficiency. Moreover, the peak efficiency is as high as 94.3% with a chip area of 1.2 \times 1.7 mm2.

AB - This article proposes a single-inductor multi-output converter implemented in 0.153 \mu{\mathrm {m}} CMOS process, including the adaptive switchable continuous conduction mode (CCM) and discontinuous conduction mode (DCM) (ASCD) technique, and a five-input crosstalk reduction error amplifier (CREA) to minimize the cross regulation to 0.03 mV/mA and achieve load capability up to 3 W. At ultra-light loads, the proposed ultralow power (ULP) mode is applied to reach 185 nA quiescent current and enhance light load power efficiency. Moreover, the peak efficiency is as high as 94.3% with a chip area of 1.2 \times 1.7 mm2.

KW - Continuous conduction mode (CCM)

KW - cross regulation

KW - discontinuous conduction mode (DCM)

KW - single-inductor multi-output (SIMO)

KW - ultralow quiescent current

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U2 - 10.1109/JSSC.2022.3142207

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M3 - Article

AN - SCOPUS:85124108051

SN - 0018-9200

VL - 57

SP - 2731

EP - 2740

JO - IEEE Journal of Solid-State Circuits

JF - IEEE Journal of Solid-State Circuits

IS - 9

ER -

A 94.3% Peak Efficiency Adaptive Switchable CCM and DCM Single-Inductor Multiple-Output Converter with 0.03 mV/mA Low Crosstalk and 185 nA Ultralow Quiescent

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