TY - GEN
T1 - A 91-dB DR 20-kHz BW 5th-Order Multi-Step Incremental ADC for Sensor Interfaces by Re-Using a MASH 2-1 Modulator
AU - Huang, Jia Sheng
AU - Kuo, Shih Che
AU - Huang, Yu Cheng
AU - Kao, Chia Wei
AU - Hsu, Che Wei
AU - Chen, Chia Hung
N1 - Publisher Copyright:
© 2022 IEEE.
PY - 2022
Y1 - 2022
N2 - Incremental ΔΣ analog-to-digital-converters (IADCs) possess indispensable advantages over conventional ΔΣ counterparts to interface the sensors. By adding global reset pulses to clear the memory in oversampled modulators and decimation filters, the reset pulses output the Nyquist-rate digitized samples. The hybrid of oversampling and Nyquist-rate conversions are thus easier to multiplex among multiple channels with very low conversion latency and much simpler decimation filters. These strengths favor the IADCs for high-resolution sensor data conversions, for example, column-parallel ADCs in image sensors and touch control panels. However, a first-order IADC (IADC1) is too slow and at least a second-order (IADC2) or a higher-order one is mandatory to shorten the conversion time and achieve good energy efficiency. To mitigate the instability of high-order IADCs and extend the non-overloaded input range, cascaded or multi-stage noise-shaping (MASH) modulators is an effective solution. In this paper, a MASH IADC (IADC2-1) incorporating an IADC2 and an IADC1 is proposed to operate in two steps by re-using and re-configuring the same circuits of IADC2-1. The third-order noise-shaping performance is boosted up to fifth-order with very low oversampling ratio (OSR) and very small area in 0.18 μm technology.
AB - Incremental ΔΣ analog-to-digital-converters (IADCs) possess indispensable advantages over conventional ΔΣ counterparts to interface the sensors. By adding global reset pulses to clear the memory in oversampled modulators and decimation filters, the reset pulses output the Nyquist-rate digitized samples. The hybrid of oversampling and Nyquist-rate conversions are thus easier to multiplex among multiple channels with very low conversion latency and much simpler decimation filters. These strengths favor the IADCs for high-resolution sensor data conversions, for example, column-parallel ADCs in image sensors and touch control panels. However, a first-order IADC (IADC1) is too slow and at least a second-order (IADC2) or a higher-order one is mandatory to shorten the conversion time and achieve good energy efficiency. To mitigate the instability of high-order IADCs and extend the non-overloaded input range, cascaded or multi-stage noise-shaping (MASH) modulators is an effective solution. In this paper, a MASH IADC (IADC2-1) incorporating an IADC2 and an IADC1 is proposed to operate in two steps by re-using and re-configuring the same circuits of IADC2-1. The third-order noise-shaping performance is boosted up to fifth-order with very low oversampling ratio (OSR) and very small area in 0.18 μm technology.
UR - http://www.scopus.com/inward/record.url?scp=85146556499&partnerID=8YFLogxK
U2 - 10.1109/A-SSCC56115.2022.9980590
DO - 10.1109/A-SSCC56115.2022.9980590
M3 - Conference contribution
AN - SCOPUS:85146556499
T3 - 2022 IEEE Asian Solid-State Circuits Conference, A-SSCC 2022 - Proceedings
SP - 2
EP - 4
BT - 2022 IEEE Asian Solid-State Circuits Conference, A-SSCC 2022 - Proceedings
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 2022 IEEE Asian Solid-State Circuits Conference, A-SSCC 2022
Y2 - 6 November 2022 through 9 November 2022
ER -
