A leading edge 90 nm bulk CMOS device technology is described in this paper. In this technology, multi Vt and multi gate oxide devices are offered to support low standby power (LP), general-purpose (G or ASIC), and high-speed (HS) system on chip (SoC) applications. High voltage I/O devices are supported using 70 A, 50 A, and 28 A gate oxide for 3.3 V, 2.5 V, and 1.5-1.8 V interfaces, respectively. The backend architecture is based on nine levels of Cu interconnect with hot black diamond (HBD) low-k dielectric (k<=3.0).
|Number of pages||4|
|Journal||Technical Digest - International Electron Devices Meeting|
|State||Published - 2002|