@inproceedings{a0cbe6c8dead4bbea25b8cf70a1e7676,
title = "A 802.15.3c/802.11ad compliant 24 Gb/s FFT processor for 60 GHz communication systems",
abstract = "This paper, we present a 24 Gb/s 512-point 8X-parallel FFT processor for 60 GHz communication systems. The proposed design is a pipelined Multipath Delay Feedback (MDF) radix-23 architecture, which exploits the parallelism of the multipath scheme together with pipeline technique to achieve a high throughput rate. Besides, the proposed FFT processor is implemented with an area efficient optimized multiplier architecture that avoid the need to store the twiddle factor in memory and a dynamic scaling technique to enhance the SQNR, allowing the FFT to operate with 16-QAM and 64-QAM for single carrier (SC) and orthogonal frequency-division multiplexing(OFDM) schemes. This FFT processor has been implemented in a SC/OFDM dual-mode baseband receiver satisfying the requirements of the 802.15.3c/802.11ad standard with a 40nm CMOS process. The post-layout implementation results show that the proposed FFT processor is able to achieve up to 24 Gb/s throughput rate at 500MHz clock with a power consumption of 87mW and area of 0.64mm2.",
author = "Davila, {Henry Lopez} and Liu, {Chun Yi} and Liu, {Wei Chang} and Huang, {Shen Jui} and Jou, {Shyh Jye} and Chen, {Sau Gee}",
note = "Publisher Copyright: {\textcopyright} 2015 IEEE.; 28th IEEE International System on Chip Conference, SOCC 2015 ; Conference date: 08-09-2015 Through 11-09-2015",
year = "2016",
month = feb,
day = "12",
doi = "10.1109/SOCC.2015.7406907",
language = "English",
series = "International System on Chip Conference",
publisher = "IEEE Computer Society",
pages = "44--48",
editor = "Thomas Buchner and Danella Zhao and Karan Bhatia and Ramalingam Sridhar",
booktitle = "Proceedings - 28th IEEE International System on Chip Conference, SOCC 2015",
address = "美國",
}