A 7.92 Gb/s 437.2 mW stochastic LDPC decoder chip for IEEE 802.15.3c applications

Keyphrases

• 90-nm CMOS Technology 25%
• Bypass Circuit 25%
• Check Node Unit 25%
• Chip Utilization 25%
• Clock Frequency 25%
• Clock Generation 25%
• CMOS Process 25%
• Code Rate 25%
• Delay-locked Loop 25%
• Encoder 25%
• Energy Efficiency 50%
• Fully Parallel 25%
• Gate Count 25%
• Hardware Efficiency 50%
• High-throughput 25%
• IEEE 802.15.3c 100%
• Information Generation 25%
• Isolated Power System 25%
• LDPC Decoder 100%
• Matrix multiplication 25%
• Measurement Uncertainty 25%
• Optimized Routing 25%
• Parity Check Matrix 25%
• Permutation Method 25%
• Power Consumption 25%
• Power Domain 25%
• Reconfigurable 25%
• Reduced Complexity 25%
• Route Network 25%
• Stochastic Arithmetic 25%
• Supply Voltage 25%
• Track Prediction 25%
• Variable Node 50%

Engineering

• Check Node 50%
• Clock Frequency 50%
• Code Rate 50%
• Critical Path 50%
• Data Rate 50%
• Delay Lock Loops 50%
• Electric Power Utilization 50%
• Energy Conservation 100%
• Energy Efficiency 100%
• Measurement Uncertainty 50%
• Multiple Code 50%
• Network Routing 50%
• Nodes 100%
• Parity Check Matrix 50%
• Supply Voltage 50%
• Test Environment 50%

Computer Science

• Clock Frequency 50%
• Computer Hardware 100%
• Critical Path 50%
• Energy Efficiency 100%
• High Throughput 50%
• Network Routing 50%
• Parity Check Matrix 50%
• Power Consumption 50%
• Supply Voltage 50%
• Test Environment 50%