A 7.72 Gb/s LDPC-CC decoder with overlapped architecture for pre-5G wireless communications

Chia Lung Lin*, Rong Jie Liu, Chih-Lung Chen, Hsie-Chia Chang, Chen-Yi Lee

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

6 Scopus citations

Abstract

LDPC block codes (LDPC-BCs) have attracted great interests in recent years by highly parallel computation and good bit-error-rate performance, and one of the decoder implementation issues is high routing complexity. LDPC convolutional codes (LDPC-CCs) not only release routing complexity but also are natural to dynamic length of data frame. Thus, the codes are very suitable for video stream and pre-5G wireless communication systems. LDPC-CC decoder is composed of several concatenated processors, where the long FIFOs are usually the bottleneck of area and decoding latency. To improve hardware efficiency, we use overlapped architecture to share partial FIFO between processors. Furthermore, check node unit and hybrid-partitioned FIFO are proposed to increase throughput and pipeline efficiency. The measurement results of test chip in 65nm technology show that our work can achieves 7.72 Gb/s under 322MHz operating frequency. The decoder with 6 processors occupies an area of 1.19 mm2, drawing 410.5 mW of power with an energy efficiency of 8.75pJ/bit/proc.

Original languageEnglish
Title of host publication2016 IEEE Asian Solid-State Circuits Conference, A-SSCC 2016 - Proceedings
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages337-340
Number of pages4
ISBN (Electronic)9781509037001
DOIs
StatePublished - 6 Feb 2017
Event12th IEEE Asian Solid-State Circuits Conference, A-SSCC 2016 - Toyama, Japan
Duration: 7 Nov 20169 Nov 2016

Publication series

Name2016 IEEE Asian Solid-State Circuits Conference, A-SSCC 2016 - Proceedings

Conference

Conference12th IEEE Asian Solid-State Circuits Conference, A-SSCC 2016
Country/TerritoryJapan
CityToyama
Period7/11/169/11/16

Keywords

  • digital signal
  • high throughput
  • LDPC
  • LDPC convolutional codes
  • overlapped architecture

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