A 7.72 Gb/s LDPC-CC decoder with overlapped architecture for pre-5G wireless communications

Chia Lung Lin; Rong Jie Liu; Chih-Lung Chen; Hsie-Chia Chang; Chen-Yi Lee

doi:10.1109/ASSCC.2016.7844204

A 7.72 Gb/s LDPC-CC decoder with overlapped architecture for pre-5G wireless communications

Chia Lung Lin^*, Rong Jie Liu, Chih-Lung Chen, Hsie-Chia Chang, Chen-Yi Lee

^*Corresponding author for this work

Institute of Electronics

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

6 Scopus citations

Abstract

LDPC block codes (LDPC-BCs) have attracted great interests in recent years by highly parallel computation and good bit-error-rate performance, and one of the decoder implementation issues is high routing complexity. LDPC convolutional codes (LDPC-CCs) not only release routing complexity but also are natural to dynamic length of data frame. Thus, the codes are very suitable for video stream and pre-5G wireless communication systems. LDPC-CC decoder is composed of several concatenated processors, where the long FIFOs are usually the bottleneck of area and decoding latency. To improve hardware efficiency, we use overlapped architecture to share partial FIFO between processors. Furthermore, check node unit and hybrid-partitioned FIFO are proposed to increase throughput and pipeline efficiency. The measurement results of test chip in 65nm technology show that our work can achieves 7.72 Gb/s under 322MHz operating frequency. The decoder with 6 processors occupies an area of 1.19 mm², drawing 410.5 mW of power with an energy efficiency of 8.75pJ/bit/proc.

Original language	English
Title of host publication	2016 IEEE Asian Solid-State Circuits Conference, A-SSCC 2016 - Proceedings
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	337-340
Number of pages	4
ISBN (Electronic)	9781509037001
DOIs	https://doi.org/10.1109/ASSCC.2016.7844204
State	Published - 6 Feb 2017
Event	12th IEEE Asian Solid-State Circuits Conference, A-SSCC 2016 - Toyama, Japan Duration: 7 Nov 2016 → 9 Nov 2016

Publication series

Name	2016 IEEE Asian Solid-State Circuits Conference, A-SSCC 2016 - Proceedings

Conference

Conference	12th IEEE Asian Solid-State Circuits Conference, A-SSCC 2016
Country/Territory	Japan
City	Toyama
Period	7/11/16 → 9/11/16

Keywords

digital signal
high throughput
LDPC
LDPC convolutional codes
overlapped architecture

UN SDGs

This output contributes to the following UN Sustainable Development Goals (SDGs)

Access to Document

10.1109/ASSCC.2016.7844204

Cite this

Lin, C. L., Liu, R. J., Chen, C.-L., Chang, H.-C., & Lee, C.-Y. (2017). A 7.72 Gb/s LDPC-CC decoder with overlapped architecture for pre-5G wireless communications. In 2016 IEEE Asian Solid-State Circuits Conference, A-SSCC 2016 - Proceedings (pp. 337-340). Article 7844204 (2016 IEEE Asian Solid-State Circuits Conference, A-SSCC 2016 - Proceedings). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ASSCC.2016.7844204

Lin, Chia Lung ; Liu, Rong Jie ; Chen, Chih-Lung et al. / A 7.72 Gb/s LDPC-CC decoder with overlapped architecture for pre-5G wireless communications. 2016 IEEE Asian Solid-State Circuits Conference, A-SSCC 2016 - Proceedings. Institute of Electrical and Electronics Engineers Inc., 2017. pp. 337-340 (2016 IEEE Asian Solid-State Circuits Conference, A-SSCC 2016 - Proceedings).

@inproceedings{840205fb412d4afc8e05d9a8ca5ae735,

title = "A 7.72 Gb/s LDPC-CC decoder with overlapped architecture for pre-5G wireless communications",

abstract = "LDPC block codes (LDPC-BCs) have attracted great interests in recent years by highly parallel computation and good bit-error-rate performance, and one of the decoder implementation issues is high routing complexity. LDPC convolutional codes (LDPC-CCs) not only release routing complexity but also are natural to dynamic length of data frame. Thus, the codes are very suitable for video stream and pre-5G wireless communication systems. LDPC-CC decoder is composed of several concatenated processors, where the long FIFOs are usually the bottleneck of area and decoding latency. To improve hardware efficiency, we use overlapped architecture to share partial FIFO between processors. Furthermore, check node unit and hybrid-partitioned FIFO are proposed to increase throughput and pipeline efficiency. The measurement results of test chip in 65nm technology show that our work can achieves 7.72 Gb/s under 322MHz operating frequency. The decoder with 6 processors occupies an area of 1.19 mm2, drawing 410.5 mW of power with an energy efficiency of 8.75pJ/bit/proc.",

keywords = "digital signal, high throughput, LDPC, LDPC convolutional codes, overlapped architecture",

author = "Lin, {Chia Lung} and Liu, {Rong Jie} and Chih-Lung Chen and Hsie-Chia Chang and Chen-Yi Lee",

year = "2017",

month = feb,

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doi = "10.1109/ASSCC.2016.7844204",

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series = "2016 IEEE Asian Solid-State Circuits Conference, A-SSCC 2016 - Proceedings",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

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booktitle = "2016 IEEE Asian Solid-State Circuits Conference, A-SSCC 2016 - Proceedings",

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note = "12th IEEE Asian Solid-State Circuits Conference, A-SSCC 2016 ; Conference date: 07-11-2016 Through 09-11-2016",

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Lin, CL, Liu, RJ, Chen, C-L, Chang, H-C & Lee, C-Y 2017, A 7.72 Gb/s LDPC-CC decoder with overlapped architecture for pre-5G wireless communications. in 2016 IEEE Asian Solid-State Circuits Conference, A-SSCC 2016 - Proceedings., 7844204, 2016 IEEE Asian Solid-State Circuits Conference, A-SSCC 2016 - Proceedings, Institute of Electrical and Electronics Engineers Inc., pp. 337-340, 12th IEEE Asian Solid-State Circuits Conference, A-SSCC 2016, Toyama, Japan, 7/11/16. https://doi.org/10.1109/ASSCC.2016.7844204

A 7.72 Gb/s LDPC-CC decoder with overlapped architecture for pre-5G wireless communications. / Lin, Chia Lung; Liu, Rong Jie; Chen, Chih-Lung et al.
2016 IEEE Asian Solid-State Circuits Conference, A-SSCC 2016 - Proceedings. Institute of Electrical and Electronics Engineers Inc., 2017. p. 337-340 7844204 (2016 IEEE Asian Solid-State Circuits Conference, A-SSCC 2016 - Proceedings).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - A 7.72 Gb/s LDPC-CC decoder with overlapped architecture for pre-5G wireless communications

AU - Lin, Chia Lung

AU - Liu, Rong Jie

AU - Chen, Chih-Lung

AU - Chang, Hsie-Chia

AU - Lee, Chen-Yi

PY - 2017/2/6

Y1 - 2017/2/6

N2 - LDPC block codes (LDPC-BCs) have attracted great interests in recent years by highly parallel computation and good bit-error-rate performance, and one of the decoder implementation issues is high routing complexity. LDPC convolutional codes (LDPC-CCs) not only release routing complexity but also are natural to dynamic length of data frame. Thus, the codes are very suitable for video stream and pre-5G wireless communication systems. LDPC-CC decoder is composed of several concatenated processors, where the long FIFOs are usually the bottleneck of area and decoding latency. To improve hardware efficiency, we use overlapped architecture to share partial FIFO between processors. Furthermore, check node unit and hybrid-partitioned FIFO are proposed to increase throughput and pipeline efficiency. The measurement results of test chip in 65nm technology show that our work can achieves 7.72 Gb/s under 322MHz operating frequency. The decoder with 6 processors occupies an area of 1.19 mm2, drawing 410.5 mW of power with an energy efficiency of 8.75pJ/bit/proc.

AB - LDPC block codes (LDPC-BCs) have attracted great interests in recent years by highly parallel computation and good bit-error-rate performance, and one of the decoder implementation issues is high routing complexity. LDPC convolutional codes (LDPC-CCs) not only release routing complexity but also are natural to dynamic length of data frame. Thus, the codes are very suitable for video stream and pre-5G wireless communication systems. LDPC-CC decoder is composed of several concatenated processors, where the long FIFOs are usually the bottleneck of area and decoding latency. To improve hardware efficiency, we use overlapped architecture to share partial FIFO between processors. Furthermore, check node unit and hybrid-partitioned FIFO are proposed to increase throughput and pipeline efficiency. The measurement results of test chip in 65nm technology show that our work can achieves 7.72 Gb/s under 322MHz operating frequency. The decoder with 6 processors occupies an area of 1.19 mm2, drawing 410.5 mW of power with an energy efficiency of 8.75pJ/bit/proc.

KW - digital signal

KW - high throughput

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KW - LDPC convolutional codes

KW - overlapped architecture

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DO - 10.1109/ASSCC.2016.7844204

M3 - Conference contribution

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SP - 337

EP - 340

BT - 2016 IEEE Asian Solid-State Circuits Conference, A-SSCC 2016 - Proceedings

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 12th IEEE Asian Solid-State Circuits Conference, A-SSCC 2016

Y2 - 7 November 2016 through 9 November 2016

ER -

Lin CL, Liu RJ, Chen CL, Chang HC , Lee CY. A 7.72 Gb/s LDPC-CC decoder with overlapped architecture for pre-5G wireless communications. In 2016 IEEE Asian Solid-State Circuits Conference, A-SSCC 2016 - Proceedings. Institute of Electrical and Electronics Engineers Inc. 2017. p. 337-340. 7844204. (2016 IEEE Asian Solid-State Circuits Conference, A-SSCC 2016 - Proceedings). doi: 10.1109/ASSCC.2016.7844204

A 7.72 Gb/s LDPC-CC decoder with overlapped architecture for pre-5G wireless communications

Abstract

Publication series

Conference

Keywords

UN SDGs

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