TY - GEN
T1 - A 75.6M Base-pairs/s FPGA Accelerator for FM-index Based Paired-end Short-Read Mapping
AU - Yang, Chung Hsuan
AU - Wu, Yi Chung
AU - Chen, Yen Lung
AU - Lee, Chao Hsi
AU - Hung, Jui Hung
AU - Yang, Chia Hsiang
N1 - Publisher Copyright:
© 2022 IEEE.
PY - 2022
Y1 - 2022
N2 - Next-generation sequencing (NGS) has been widely applied to genetics research and biomedical applications. It achieves a high sequencing speed by sequencing subsequences (called short-reads) in a massively parallel manner [1]. However, the succeeding data analysis for assembling short-reads still takes a couple of days on CPU and thus becomes the bottleneck. Fig. 1(a) shows the NGS data analysis workflow, consisting of short-read mapping, haplotype & variant calling, and genotype calling. Of these three steps, the execution time is dominated by short-read mapping. A CPU-FPGA heterogeneous system is presented in [2] for accelerating short-read mapping, but the performance improvement is limited. A dedicated FPGA accelerator [3] achieves a higher throughput at a cost of a larger DRAM requirement. Compared to prior arts, this work presents an FPGA accelerator that delivers a 1.7-to-18.6x higher throughput in a memory-efficient way. Paired-end short-read mapping is exploited to achieve the highest 99.3% accuracy on true human DNA.
AB - Next-generation sequencing (NGS) has been widely applied to genetics research and biomedical applications. It achieves a high sequencing speed by sequencing subsequences (called short-reads) in a massively parallel manner [1]. However, the succeeding data analysis for assembling short-reads still takes a couple of days on CPU and thus becomes the bottleneck. Fig. 1(a) shows the NGS data analysis workflow, consisting of short-read mapping, haplotype & variant calling, and genotype calling. Of these three steps, the execution time is dominated by short-read mapping. A CPU-FPGA heterogeneous system is presented in [2] for accelerating short-read mapping, but the performance improvement is limited. A dedicated FPGA accelerator [3] achieves a higher throughput at a cost of a larger DRAM requirement. Compared to prior arts, this work presents an FPGA accelerator that delivers a 1.7-to-18.6x higher throughput in a memory-efficient way. Paired-end short-read mapping is exploited to achieve the highest 99.3% accuracy on true human DNA.
UR - http://www.scopus.com/inward/record.url?scp=85146580614&partnerID=8YFLogxK
U2 - 10.1109/A-SSCC56115.2022.9980714
DO - 10.1109/A-SSCC56115.2022.9980714
M3 - Conference contribution
AN - SCOPUS:85146580614
T3 - 2022 IEEE Asian Solid-State Circuits Conference, A-SSCC 2022 - Proceedings
BT - 2022 IEEE Asian Solid-State Circuits Conference, A-SSCC 2022 - Proceedings
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 2022 IEEE Asian Solid-State Circuits Conference, A-SSCC 2022
Y2 - 6 November 2022 through 9 November 2022
ER -