A 75.6M Base-pairs/s FPGA Accelerator for FM-index Based Paired-end Short-Read Mapping

Chung Hsuan Yang, Yi Chung Wu, Yen Lung Chen, Chao Hsi Lee, Jui Hung Hung, Chia Hsiang Yang

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

1 Scopus citations

Abstract

Next-generation sequencing (NGS) has been widely applied to genetics research and biomedical applications. It achieves a high sequencing speed by sequencing subsequences (called short-reads) in a massively parallel manner [1]. However, the succeeding data analysis for assembling short-reads still takes a couple of days on CPU and thus becomes the bottleneck. Fig. 1(a) shows the NGS data analysis workflow, consisting of short-read mapping, haplotype & variant calling, and genotype calling. Of these three steps, the execution time is dominated by short-read mapping. A CPU-FPGA heterogeneous system is presented in [2] for accelerating short-read mapping, but the performance improvement is limited. A dedicated FPGA accelerator [3] achieves a higher throughput at a cost of a larger DRAM requirement. Compared to prior arts, this work presents an FPGA accelerator that delivers a 1.7-to-18.6x higher throughput in a memory-efficient way. Paired-end short-read mapping is exploited to achieve the highest 99.3% accuracy on true human DNA.

Original languageEnglish
Title of host publication2022 IEEE Asian Solid-State Circuits Conference, A-SSCC 2022 - Proceedings
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9781665471435
DOIs
StatePublished - 2022
Event2022 IEEE Asian Solid-State Circuits Conference, A-SSCC 2022 - Taipei, Taiwan
Duration: 6 Nov 20229 Nov 2022

Publication series

Name2022 IEEE Asian Solid-State Circuits Conference, A-SSCC 2022 - Proceedings

Conference

Conference2022 IEEE Asian Solid-State Circuits Conference, A-SSCC 2022
Country/TerritoryTaiwan
CityTaipei
Period6/11/229/11/22

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