A 7.11mJ/Gb/query data-driven machine learning processor (D2MLP) for big data analysis and applications

Chang Hung Tsai; Tung Yu Wu; Shu Yu Hsu; Chia Ching Chu; Fang Ju Ku; Ying Siou Laio; Chih Lung Chen; Wing Hung Wong; Hsie-Chia Chang; Chen-Yi Lee

doi:10.1109/VLSIC.2014.6858422

A 7.11mJ/Gb/query data-driven machine learning processor (D²MLP) for big data analysis and applications

Chang Hung Tsai, Tung Yu Wu, Shu Yu Hsu, Chia Ching Chu, Fang Ju Ku, Ying Siou Laio, Chih Lung Chen, Wing Hung Wong, Hsie-Chia Chang, Chen-Yi Lee

Institute of Electronics

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

3 Scopus citations

Abstract

A data-driven machine learning processor (D²MLP) with MIMD architecture is designed for big data analysis. Adopting the configurable counting engine array with 3-layer dimension merging, the D²MLP processes maximal 1-128/1024 dimensional data with parallel 64/8 queries in learning stage. Implement in 90nm CMOS technology, the D²MLP achieves 219.9x and 8.2x faster processing time than CPU and GPGPU, respectively. In application phase, maximal 22.7k 128-class classifications/s are performed with the learned density model. Operated at 1.0V and 165MHz, the D²MLP demonstrates an energy-efficient solution for learning and classification with 7.11mJ/Gb/query and 2.3μJ/classification, respectively.

Original language	English
Title of host publication	2014 Symposium on VLSI Circuits, VLSIC 2014 - Digest of Technical Papers
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Print)	9781479933273
DOIs	https://doi.org/10.1109/VLSIC.2014.6858422
State	Published - 1 Jan 2014
Event	28th IEEE Symposium on VLSI Circuits, VLSIC 2014 - Honolulu, HI, United States Duration: 10 Jun 2014 → 13 Jun 2014

Publication series

Name	IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Conference

Conference	28th IEEE Symposium on VLSI Circuits, VLSIC 2014
Country/Territory	United States
City	Honolulu, HI
Period	10/06/14 → 13/06/14

Access to Document

10.1109/VLSIC.2014.6858422

Cite this

Tsai, C. H., Wu, T. Y., Hsu, S. Y., Chu, C. C., Ku, F. J., Laio, Y. S., Chen, C. L., Wong, W. H., Chang, H.-C., & Lee, C.-Y. (2014). A 7.11mJ/Gb/query data-driven machine learning processor (D²MLP) for big data analysis and applications. In 2014 Symposium on VLSI Circuits, VLSIC 2014 - Digest of Technical Papers Article 6858422 (IEEE Symposium on VLSI Circuits, Digest of Technical Papers). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/VLSIC.2014.6858422

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abstract = "A data-driven machine learning processor (D2MLP) with MIMD architecture is designed for big data analysis. Adopting the configurable counting engine array with 3-layer dimension merging, the D2MLP processes maximal 1-128/1024 dimensional data with parallel 64/8 queries in learning stage. Implement in 90nm CMOS technology, the D2MLP achieves 219.9x and 8.2x faster processing time than CPU and GPGPU, respectively. In application phase, maximal 22.7k 128-class classifications/s are performed with the learned density model. Operated at 1.0V and 165MHz, the D2MLP demonstrates an energy-efficient solution for learning and classification with 7.11mJ/Gb/query and 2.3μJ/classification, respectively.",

author = "Tsai, {Chang Hung} and Wu, {Tung Yu} and Hsu, {Shu Yu} and Chu, {Chia Ching} and Ku, {Fang Ju} and Laio, {Ying Siou} and Chen, {Chih Lung} and Wong, {Wing Hung} and Hsie-Chia Chang and Chen-Yi Lee",

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Tsai, CH, Wu, TY, Hsu, SY, Chu, CC, Ku, FJ, Laio, YS, Chen, CL, Wong, WH, Chang, H-C & Lee, C-Y 2014, A 7.11mJ/Gb/query data-driven machine learning processor (D²MLP) for big data analysis and applications. in 2014 Symposium on VLSI Circuits, VLSIC 2014 - Digest of Technical Papers., 6858422, IEEE Symposium on VLSI Circuits, Digest of Technical Papers, Institute of Electrical and Electronics Engineers Inc., 28th IEEE Symposium on VLSI Circuits, VLSIC 2014, Honolulu, HI, United States, 10/06/14. https://doi.org/10.1109/VLSIC.2014.6858422

A 7.11mJ/Gb/query data-driven machine learning processor (D²MLP) for big data analysis and applications. / Tsai, Chang Hung; Wu, Tung Yu; Hsu, Shu Yu et al.
2014 Symposium on VLSI Circuits, VLSIC 2014 - Digest of Technical Papers. Institute of Electrical and Electronics Engineers Inc., 2014. 6858422 (IEEE Symposium on VLSI Circuits, Digest of Technical Papers).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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Tsai CH, Wu TY, Hsu SY, Chu CC, Ku FJ, Laio YS et al. A 7.11mJ/Gb/query data-driven machine learning processor (D²MLP) for big data analysis and applications. In 2014 Symposium on VLSI Circuits, VLSIC 2014 - Digest of Technical Papers. Institute of Electrical and Electronics Engineers Inc. 2014. 6858422. (IEEE Symposium on VLSI Circuits, Digest of Technical Papers). doi: 10.1109/VLSIC.2014.6858422