Abstract
A 10 GHz all digital frequency synthesizer (ADPLL) with dynamic digital loop filter is presented. Governed by a proposed locking process monitor (LPM), the digital loop filter is automatically reconfigured during the frequency acquisition and phase tracking process. The loop bandwidth is also self-adjusted during the locking process so as to achieve fast lock and low noise simultaneously. A skew-compensated phase accumulator is proposed for high speed operation, which preserves the advantages of low power dissipation while eliminating the accumulated timing skew issue. With less than 7 μs locking time, the measured rms jitter from a 9.92 GHz carrier is about 0.9 ps. The ADPLL core consumes 7.1 mW from a 1 V supply, and the digital I/O cells drains 2.7 mW from a 3.3 V supply for chip measurement. Implemented in a 90 nm CMOS technology, the core area is only 0.352 mm 2.
Original language | English |
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Article number | 5419178 |
Pages (from-to) | 578-586 |
Number of pages | 9 |
Journal | IEEE Journal of Solid-State Circuits |
Volume | 45 |
Issue number | 3 |
DOIs | |
State | Published - 1 Mar 2010 |
Keywords
- ADPLL
- Bang-bang phase detector
- Frequency divider
- Phase accumulator
- Phase-frequency detector
- Phase-locked loop