A 65nm Node Strained SOI Technology with Slim Spacer

Fu Liang Yang*, Chien Chao Huang, Hou Yu Chen, Jhon Jhy Liaw, Tang Xuan Chung, Hung Wei Chen, Chang Yun Chang, Cheng Chuan Huang, Kuang Hsin Chen, Di Hong Lee, Hsun Chih Tsao, Cheng Kuo Wen, Shui Ming Cheng, Yi Ming Sheu, Ke Wei Su, Chi Chun Chen, Tze Liang Lee, Shih Chang Chen, Chih Jian Chen, Cheng Hung ChangJhi Cheng Lu, Weng Chang, Chuan Ping Hou, Ying Ho Chen, Kuei Shun Chen, Ming Lu, Li Wei Kung, Yu Jun Chou, Fu Jye Liang, Jan Wen You, King Chang Shu, Bin Chang Chang, Jaw Jung Shin, Chun Kuang Chen, Tsai Sheng Gau, Bor Wen Chan, Yi Chun Huang, Han Jan Tao, Jyh Huei Chen, Yung Shun Chen, Yee Chia Yeo, Samuel K.H. Fung, Carlos H. Diaz, Chii Ming M. Wu, Burn J. Lin, Mong Song Liang, Jack Y.C. Sun, Chen-Ming Hu

*Corresponding author for this work

Research output: Contribution to journalConference articlepeer-review

12 Scopus citations


A 65 nm node strained SOI technology with high performance is demonstrated, providing drive currents of 1015 and 500 μA/μm for N-FET and P-FET, respectively, at an off-state leakage of 40 nA/μm using 1 V operation. The technology employs an aggressively scaled slim spacer of 30 nm width to amplify stress benefits for performance improvement, and to reduce 10-20% layout area for SRAM-cell-like circuits, while maintaining excellent hot carrier immunity and well-controlled short-channel effects. For the first time, we demonstrate that FinFET devices, implicitly implemented in this technology, offer a 8-15% higher inverter speed compared to planar SOI devices at the same drive current.

Original languageEnglish
Pages (from-to)627-630
Number of pages4
JournalTechnical Digest - International Electron Devices Meeting
StatePublished - 1 Dec 2003
EventIEEE International Electron Devices Meeting - Washington, DC, United States
Duration: 8 Dec 200310 Dec 2003


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