A 650 pW,-71 dB PSRR, 205°C Temperature Range Hybrid Voltage Reference with Curvature-Based Temperature Compensation and SBFL Techniques

Cheng Ze Shao; Yu-Te Liao

doi:10.23919/VLSICircuits52068.2021.9492407

A 650 pW,-71 dB PSRR, 205°C Temperature Range Hybrid Voltage Reference with Curvature-Based Temperature Compensation and SBFL Techniques

Cheng Ze Shao, Yu-Te Liao

Department of Electrical and Computer Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

3 Scopus citations

Abstract

This paper presents a 650 pW 1V hybrid voltage reference with curvature-based temperature compensation in a 0.18-μm CMOS process. The design achieves a 45 ppm/°C from-55 to 150 °C, line sensitivity of 0.016 %/V and PSRR of-71 dB at 100 Hz by employing a self-biasing feedback loop.

Original language	English
Title of host publication	2021 Symposium on VLSI Circuits, VLSI Circuits 2021
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)	9784863487796
DOIs	https://doi.org/10.23919/VLSICircuits52068.2021.9492407
State	Published - 13 Jun 2021
Event	35th Symposium on VLSI Circuits, VLSI Circuits 2021 - Virutal, Online Duration: 13 Jun 2021 → 19 Jun 2021

Publication series

Name	IEEE Symposium on VLSI Circuits, Digest of Technical Papers
Volume	2021-June

Conference

Conference	35th Symposium on VLSI Circuits, VLSI Circuits 2021
City	Virutal, Online
Period	13/06/21 → 19/06/21

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10.23919/VLSICircuits52068.2021.9492407

Cite this

Shao, C. Z., & Liao, Y.-T. (2021). A 650 pW,-71 dB PSRR, 205°C Temperature Range Hybrid Voltage Reference with Curvature-Based Temperature Compensation and SBFL Techniques. In 2021 Symposium on VLSI Circuits, VLSI Circuits 2021 Article 9492407 (IEEE Symposium on VLSI Circuits, Digest of Technical Papers; Vol. 2021-June). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.23919/VLSICircuits52068.2021.9492407

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abstract = "This paper presents a 650 pW 1V hybrid voltage reference with curvature-based temperature compensation in a 0.18-μm CMOS process. The design achieves a 45 ppm/°C from-55 to 150 °C, line sensitivity of 0.016 %/V and PSRR of-71 dB at 100 Hz by employing a self-biasing feedback loop.",

author = "Shao, {Cheng Ze} and Yu-Te Liao",

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year = "2021",

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Shao, CZ & Liao, Y-T 2021, A 650 pW,-71 dB PSRR, 205°C Temperature Range Hybrid Voltage Reference with Curvature-Based Temperature Compensation and SBFL Techniques. in 2021 Symposium on VLSI Circuits, VLSI Circuits 2021., 9492407, IEEE Symposium on VLSI Circuits, Digest of Technical Papers, vol. 2021-June, Institute of Electrical and Electronics Engineers Inc., 35th Symposium on VLSI Circuits, VLSI Circuits 2021, Virutal, Online, 13/06/21. https://doi.org/10.23919/VLSICircuits52068.2021.9492407

A 650 pW,-71 dB PSRR, 205°C Temperature Range Hybrid Voltage Reference with Curvature-Based Temperature Compensation and SBFL Techniques. / Shao, Cheng Ze; Liao, Yu-Te.
2021 Symposium on VLSI Circuits, VLSI Circuits 2021. Institute of Electrical and Electronics Engineers Inc., 2021. 9492407 (IEEE Symposium on VLSI Circuits, Digest of Technical Papers; Vol. 2021-June).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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N2 - This paper presents a 650 pW 1V hybrid voltage reference with curvature-based temperature compensation in a 0.18-μm CMOS process. The design achieves a 45 ppm/°C from-55 to 150 °C, line sensitivity of 0.016 %/V and PSRR of-71 dB at 100 Hz by employing a self-biasing feedback loop.

AB - This paper presents a 650 pW 1V hybrid voltage reference with curvature-based temperature compensation in a 0.18-μm CMOS process. The design achieves a 45 ppm/°C from-55 to 150 °C, line sensitivity of 0.016 %/V and PSRR of-71 dB at 100 Hz by employing a self-biasing feedback loop.

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T3 - IEEE Symposium on VLSI Circuits, Digest of Technical Papers

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PB - Institute of Electrical and Electronics Engineers Inc.

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Shao CZ, Liao YT. A 650 pW,-71 dB PSRR, 205°C Temperature Range Hybrid Voltage Reference with Curvature-Based Temperature Compensation and SBFL Techniques. In 2021 Symposium on VLSI Circuits, VLSI Circuits 2021. Institute of Electrical and Electronics Engineers Inc. 2021. 9492407. (IEEE Symposium on VLSI Circuits, Digest of Technical Papers). doi: 10.23919/VLSICircuits52068.2021.9492407

A 650 pW,-71 dB PSRR, 205°C Temperature Range Hybrid Voltage Reference with Curvature-Based Temperature Compensation and SBFL Techniques

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