A 650 pW,-71 dB PSRR, 205°C Temperature Range Hybrid Voltage Reference with Curvature-Based Temperature Compensation and SBFL Techniques

Cheng Ze Shao, Yu-Te Liao

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

3 Scopus citations

Abstract

This paper presents a 650 pW 1V hybrid voltage reference with curvature-based temperature compensation in a 0.18-μm CMOS process. The design achieves a 45 ppm/°C from-55 to 150 °C, line sensitivity of 0.016 %/V and PSRR of-71 dB at 100 Hz by employing a self-biasing feedback loop.

Original languageEnglish
Title of host publication2021 Symposium on VLSI Circuits, VLSI Circuits 2021
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9784863487796
DOIs
StatePublished - 13 Jun 2021
Event35th Symposium on VLSI Circuits, VLSI Circuits 2021 - Virutal, Online
Duration: 13 Jun 202119 Jun 2021

Publication series

NameIEEE Symposium on VLSI Circuits, Digest of Technical Papers
Volume2021-June

Conference

Conference35th Symposium on VLSI Circuits, VLSI Circuits 2021
CityVirutal, Online
Period13/06/2119/06/21

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