A 5.8 mW Continuous-Time ΔΣ Modulator with 20 MHz Bandwidth Using Time-Domain Flash Quantizer

Zong Yi Chen, Chung-Chih Hung

Research output: Contribution to journalArticlepeer-review

2 Scopus citations


This paper presents a power-efficient realization of a third-order continuous-time delta-sigma Δmodulator with 3-bit time-domain flash quantizer (TDFQ) and data-weighted averaging (DWA) based on the shifter output and input. Using the time-domain quantizer can overcome design issues in low voltage supply during CMOS downscaling. The CT-ΔΣ modulator uses the TDFQ instead of a voltage-domain quantizer to reduce power consumption. The proposed TDFQ solves the linearity problem of the delay-based voltage-to-time converter (VTC) without calibration circuit while also increasing the quantizer input range and saving energy. Moreover, in order to reduce the mismatch effects of a multibit DAC and achieve low power consumption, implementation of a low-power DWA circuit is proposed without using a digital adder to calculate pointer for controlling barrel shift circuit. This chip was fabricated in CMOS 90 nm process. The proposed CT-ΔΣ modulator consumes 5.8 mW from 1.0 V and achieves peak SNDR of 65.3 dB over the 20 MHz bandwidth, which results in FOMw = 96.3$ fJ/level and FOMS} = 161$ dB.

Original languageEnglish
Article number7343756
Pages (from-to)574-583
Number of pages10
JournalIEEE Journal on Emerging and Selected Topics in Circuits and Systems
Issue number4
StatePublished - Dec 2015


  • Analog-to-digital converter
  • continuous-time
  • data weighted averaging
  • delta-sigma modulator
  • low power
  • time-domain flash quantizer
  • voltage-to-time converter


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