A 5.7Gbps row-based layered scheduling LDPC decoder for IEEE 802.15.3c applications

Shiang Yu Hung; Shao Wei Yen; Chih Lung Chen; Hsie-Chia Chang; Shyh-Jye Jou; Chen-Yi Lee

doi:10.1109/ASSCC.2010.5716617

A 5.7Gbps row-based layered scheduling LDPC decoder for IEEE 802.15.3c applications

Shiang Yu Hung^*
, Shao Wei Yen
, Chih Lung Chen
, Hsie-Chia Chang
, Shyh-Jye Jou
, Chen-Yi Lee

^*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

11 Scopus citations

Abstract

A LDPC decoder chip supporting four code rates of IEEE 802.15.3c applications is presented. The row-based layered scheduling with normalized min-sum algorithm is proposed to reduce the iteration number while maintaining similar performance. In addition, the reconfigurable 8/16/32-input sorter is designed to deal with four LDPC codes. In order to alleviate routing complexity, both of the reallocation of sorter inputs and pre-coding routing network are proposed to reduce the input numbers of multiplexers by 64%. Fabricated in 65-nm 1P10M CMOS process, this test chip can achieve maximum 5.79Gbps throughput for the highest code rate code while the hardware efficiency and energy efficiency are 3.7Gbps/mm² and 62.4pJ/bit, respectively.

Original language	English
Title of host publication	2010 IEEE Asian Solid-State Circuits Conference, A-SSCC 2010
Pages	309-312
Number of pages	4
DOIs	https://doi.org/10.1109/ASSCC.2010.5716617
State	Published - 1 Dec 2010
Event	2010 6th IEEE Asian Solid-State Circuits Conference, A-SSCC 2010 - Beijing, China Duration: 8 Nov 2010 → 10 Nov 2010

Publication series

Name	2010 IEEE Asian Solid-State Circuits Conference, A-SSCC 2010

Conference

Conference	2010 6th IEEE Asian Solid-State Circuits Conference, A-SSCC 2010
Country/Territory	China
City	Beijing
Period	8/11/10 → 10/11/10

UN SDGs

This output contributes to the following UN Sustainable Development Goals (SDGs)

SDG 7 Affordable and Clean Energy

Access to Document

10.1109/ASSCC.2010.5716617

Cite this

Hung, S. Y., Yen, S. W., Chen, C. L., Chang, H.-C., Jou, S.-J., & Lee, C.-Y. (2010). A 5.7Gbps row-based layered scheduling LDPC decoder for IEEE 802.15.3c applications. In 2010 IEEE Asian Solid-State Circuits Conference, A-SSCC 2010 (pp. 309-312). Article 5716617 (2010 IEEE Asian Solid-State Circuits Conference, A-SSCC 2010). https://doi.org/10.1109/ASSCC.2010.5716617

@inproceedings{5631dd5553404733b088263e9df530a5,

title = "A 5.7Gbps row-based layered scheduling LDPC decoder for IEEE 802.15.3c applications",

abstract = "A LDPC decoder chip supporting four code rates of IEEE 802.15.3c applications is presented. The row-based layered scheduling with normalized min-sum algorithm is proposed to reduce the iteration number while maintaining similar performance. In addition, the reconfigurable 8/16/32-input sorter is designed to deal with four LDPC codes. In order to alleviate routing complexity, both of the reallocation of sorter inputs and pre-coding routing network are proposed to reduce the input numbers of multiplexers by 64\%. Fabricated in 65-nm 1P10M CMOS process, this test chip can achieve maximum 5.79Gbps throughput for the highest code rate code while the hardware efficiency and energy efficiency are 3.7Gbps/mm2 and 62.4pJ/bit, respectively.",

author = "Hung, \{Shiang Yu\} and Yen, \{Shao Wei\} and Chen, \{Chih Lung\} and Hsie-Chia Chang and Shyh-Jye Jou and Chen-Yi Lee",

year = "2010",

month = dec,

day = "1",

doi = "10.1109/ASSCC.2010.5716617",

language = "English",

isbn = "9781424482979",

series = "2010 IEEE Asian Solid-State Circuits Conference, A-SSCC 2010",

pages = "309--312",

booktitle = "2010 IEEE Asian Solid-State Circuits Conference, A-SSCC 2010",

note = "2010 6th IEEE Asian Solid-State Circuits Conference, A-SSCC 2010 ; Conference date: 08-11-2010 Through 10-11-2010",

}

Hung, SY, Yen, SW, Chen, CL, Chang, H-C , Jou, S-J & Lee, C-Y 2010, A 5.7Gbps row-based layered scheduling LDPC decoder for IEEE 802.15.3c applications. in 2010 IEEE Asian Solid-State Circuits Conference, A-SSCC 2010., 5716617, 2010 IEEE Asian Solid-State Circuits Conference, A-SSCC 2010, pp. 309-312, 2010 6th IEEE Asian Solid-State Circuits Conference, A-SSCC 2010, Beijing, China, 8/11/10. https://doi.org/10.1109/ASSCC.2010.5716617

A 5.7Gbps row-based layered scheduling LDPC decoder for IEEE 802.15.3c applications. / Hung, Shiang Yu; Yen, Shao Wei; Chen, Chih Lung et al.
2010 IEEE Asian Solid-State Circuits Conference, A-SSCC 2010. 2010. p. 309-312 5716617 (2010 IEEE Asian Solid-State Circuits Conference, A-SSCC 2010).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - A 5.7Gbps row-based layered scheduling LDPC decoder for IEEE 802.15.3c applications

AU - Hung, Shiang Yu

AU - Yen, Shao Wei

AU - Chen, Chih Lung

AU - Chang, Hsie-Chia

AU - Jou, Shyh-Jye

AU - Lee, Chen-Yi

PY - 2010/12/1

Y1 - 2010/12/1

N2 - A LDPC decoder chip supporting four code rates of IEEE 802.15.3c applications is presented. The row-based layered scheduling with normalized min-sum algorithm is proposed to reduce the iteration number while maintaining similar performance. In addition, the reconfigurable 8/16/32-input sorter is designed to deal with four LDPC codes. In order to alleviate routing complexity, both of the reallocation of sorter inputs and pre-coding routing network are proposed to reduce the input numbers of multiplexers by 64%. Fabricated in 65-nm 1P10M CMOS process, this test chip can achieve maximum 5.79Gbps throughput for the highest code rate code while the hardware efficiency and energy efficiency are 3.7Gbps/mm2 and 62.4pJ/bit, respectively.

AB - A LDPC decoder chip supporting four code rates of IEEE 802.15.3c applications is presented. The row-based layered scheduling with normalized min-sum algorithm is proposed to reduce the iteration number while maintaining similar performance. In addition, the reconfigurable 8/16/32-input sorter is designed to deal with four LDPC codes. In order to alleviate routing complexity, both of the reallocation of sorter inputs and pre-coding routing network are proposed to reduce the input numbers of multiplexers by 64%. Fabricated in 65-nm 1P10M CMOS process, this test chip can achieve maximum 5.79Gbps throughput for the highest code rate code while the hardware efficiency and energy efficiency are 3.7Gbps/mm2 and 62.4pJ/bit, respectively.

UR - https://www.scopus.com/pages/publications/79952824763

U2 - 10.1109/ASSCC.2010.5716617

DO - 10.1109/ASSCC.2010.5716617

M3 - Conference contribution

AN - SCOPUS:79952824763

SN - 9781424482979

T3 - 2010 IEEE Asian Solid-State Circuits Conference, A-SSCC 2010

SP - 309

EP - 312

BT - 2010 IEEE Asian Solid-State Circuits Conference, A-SSCC 2010

T2 - 2010 6th IEEE Asian Solid-State Circuits Conference, A-SSCC 2010

Y2 - 8 November 2010 through 10 November 2010

ER -

A 5.7Gbps row-based layered scheduling LDPC decoder for IEEE 802.15.3c applications

Abstract

Publication series

Conference

UN SDGs

Access to Document

Other files and links

Fingerprint

Cite this