A 5.79-Gb/s energy-efficient multirate LDPC codec chip for IEEE 802.15.3c applications

Keyphrases

• CMOS Process 50%
• Code Rate 100%
• Code Structure 50%
• Codec 100%
• Energy Efficiency 50%
• Energy Efficient 100%
• Hardware Complexity 50%
• Hardware Efficiency 50%
• IEEE 802.15.3c 100%
• Input Reallocation 50%
• Input Reduction 50%
• Layered Scheduling 50%
• LDPC Codes 50%
• LDPC Decoder 50%
• LDPC Encoder 50%
• Multi-rate 100%
• Multiplexer 50%
• Normalized Min-sum Algorithm 50%
• Number of Iterations 50%
• Parity Check Matrix 50%
• Reconfigurable 50%
• Routing Switch 50%
• Shift Register Circuit 50%
• Sorter 100%
• Unique Code 50%

Computer Science

• Computer Hardware 100%
• Energy Efficiency 50%
• Energy Efficient 100%
• min-sum algorithm 50%
• Multiplexer 50%
• Parity Check Matrix 50%
• Shift Register 50%