A 5.79-Gb/s energy-efficient multirate LDPC codec chip for IEEE 802.15.3c applications

Keyphrases

• Energy Efficient 100%
• Sorter 100%
• Code Rate 100%
• Multi-rate 100%
• LDPC Codec 100%
• Energy Efficiency 50%
• CMOS Process 50%
• Multiplexer 50%
• LDPC Decoder 50%
• Hardware Efficiency 50%
• Number of Iterations 50%
• LDPC Codes 50%
• Layered Scheduling 50%
• Normalized Min-sum Algorithm 50%
• Hardware Complexity 50%
• Code Structure 50%
• Parity Check Matrix 50%
• Routing Switch 50%
• Shift Register Circuit 50%
• Input Reallocation 50%
• LDPC Encoder 50%
• Input Reduction 50%
• Unique Code 50%
• Reconfigurable 50%

Computer Science

• Energy Efficient 100%
• Energy Efficiency 100%
• min-sum algorithm 100%
• Multiplexer 100%
• Parity Check Matrix 100%
• Shift Register 100%

Engineering

• Code Rate 100%
• Adders 50%
• Hardware Complexity 50%
• Shift Register 50%
• Parity Check Matrix 50%
• Multiplexer 50%
• Iteration Number 50%
• Conservation of Energy 50%