A 5.79-Gb/s energy-efficient multirate LDPC codec chip for IEEE 802.15.3c applications

Shao Wei Yen; Shiang Yu Hung; Chih Lung Chen; Hsie-Chia Chang; Shyh-Jye Jou; Chen-Yi Lee

doi:10.1109/JSSC.2012.2194176

A 5.79-Gb/s energy-efficient multirate LDPC codec chip for IEEE 802.15.3c applications

Shao Wei Yen^*, Shiang Yu Hung, Chih Lung Chen, Hsie-Chia Chang, Shyh-Jye Jou, Chen-Yi Lee

^*Corresponding author for this work

Research output: Contribution to journal › Article › peer-review

52 Scopus citations

Abstract

An LDPC codec chip supporting four code rates of IEEE 802.15.3c applications is presented. After utilizing row-based layered scheduling, the normalized min-sum (NMS) algorithm can reduce half of the iteration number while maintaining similar performance. According to the unique code structure of the parity-check matrix, a reconfigurable 8/16/32-input sorter is designed to deal with LDPC codes in four different code rates. Both sorter input reallocation and pre-coded routing switch are proposed to alleviate routing complexity, leading to 64% input reduction of multiplexers. In addition, an adder-accumulator-shift register (AASR) circuit is proposed for the LDPC encoder to reduce hardware complexity. After implemented in 65-nm 1P10M CMOS process, the proposed LDPC decoder chip can achieve maximum 5.79-Gb/s throughput with the hardware efficiency of 3.7 Gb/s/mm ² and energy efficiency of 62.4 pJ/b, respectively.

Original language	English
Article number	6198294
Pages (from-to)	2246-2257
Number of pages	12
Journal	IEEE Journal of Solid-State Circuits
Volume	47
Issue number	9
DOIs	https://doi.org/10.1109/JSSC.2012.2194176
State	Published - 2012

Keywords

IEEE 802.15.3c
low-density parity-check (LDPC) codes
row-based layered scheduling

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This output contributes to the following UN Sustainable Development Goals (SDGs)

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10.1109/JSSC.2012.2194176

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title = "A 5.79-Gb/s energy-efficient multirate LDPC codec chip for IEEE 802.15.3c applications",

abstract = "An LDPC codec chip supporting four code rates of IEEE 802.15.3c applications is presented. After utilizing row-based layered scheduling, the normalized min-sum (NMS) algorithm can reduce half of the iteration number while maintaining similar performance. According to the unique code structure of the parity-check matrix, a reconfigurable 8/16/32-input sorter is designed to deal with LDPC codes in four different code rates. Both sorter input reallocation and pre-coded routing switch are proposed to alleviate routing complexity, leading to 64% input reduction of multiplexers. In addition, an adder-accumulator-shift register (AASR) circuit is proposed for the LDPC encoder to reduce hardware complexity. After implemented in 65-nm 1P10M CMOS process, the proposed LDPC decoder chip can achieve maximum 5.79-Gb/s throughput with the hardware efficiency of 3.7 Gb/s/mm 2 and energy efficiency of 62.4 pJ/b, respectively.",

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year = "2012",

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AU - Chang, Hsie-Chia

AU - Jou, Shyh-Jye

AU - Lee, Chen-Yi

PY - 2012

Y1 - 2012

N2 - An LDPC codec chip supporting four code rates of IEEE 802.15.3c applications is presented. After utilizing row-based layered scheduling, the normalized min-sum (NMS) algorithm can reduce half of the iteration number while maintaining similar performance. According to the unique code structure of the parity-check matrix, a reconfigurable 8/16/32-input sorter is designed to deal with LDPC codes in four different code rates. Both sorter input reallocation and pre-coded routing switch are proposed to alleviate routing complexity, leading to 64% input reduction of multiplexers. In addition, an adder-accumulator-shift register (AASR) circuit is proposed for the LDPC encoder to reduce hardware complexity. After implemented in 65-nm 1P10M CMOS process, the proposed LDPC decoder chip can achieve maximum 5.79-Gb/s throughput with the hardware efficiency of 3.7 Gb/s/mm 2 and energy efficiency of 62.4 pJ/b, respectively.

AB - An LDPC codec chip supporting four code rates of IEEE 802.15.3c applications is presented. After utilizing row-based layered scheduling, the normalized min-sum (NMS) algorithm can reduce half of the iteration number while maintaining similar performance. According to the unique code structure of the parity-check matrix, a reconfigurable 8/16/32-input sorter is designed to deal with LDPC codes in four different code rates. Both sorter input reallocation and pre-coded routing switch are proposed to alleviate routing complexity, leading to 64% input reduction of multiplexers. In addition, an adder-accumulator-shift register (AASR) circuit is proposed for the LDPC encoder to reduce hardware complexity. After implemented in 65-nm 1P10M CMOS process, the proposed LDPC decoder chip can achieve maximum 5.79-Gb/s throughput with the hardware efficiency of 3.7 Gb/s/mm 2 and energy efficiency of 62.4 pJ/b, respectively.

KW - IEEE 802.15.3c

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A 5.79-Gb/s energy-efficient multirate LDPC codec chip for IEEE 802.15.3c applications

Abstract

Keywords

UN SDGs

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