A 521-bit dual-field elliptic curve cryptographic processor with power analysis resistance

Jen Wei Lee*, Yao Lin Chen, Chih Yeh Tseng, Hsie-Chia Chang, Chen-Yi Lee

*Corresponding author for this work

    Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

    28 Scopus citations

    Abstract

    Recently, several hardware implementations for elliptic curve cryptography have been proposed but few of them considered the dual-field functions, real-time requirement, hardware efficiency, and power analysis resistance as a whole. In this paper, a new unified division algorithm and a free pre-computation scheme are introduced to accelerate the GF(p)/GF(2n) elliptic curve arithmetic functions. The overall hardware is optimized by a very compact Galois field arithmetic unit with the fully pipelined technique. Moreover, a key-blinded technique with regular calculation is designed against the power analysis attacks without degrading clock speed. After fabricated in 90nm CMOS 1P9M process, our ECC processor occupied 0.55mm2 can perform the scalar multiplication in 19.2ms over GF(p521) and 8.2ms over GF(2409), respectively.

    Original languageEnglish
    Title of host publicationESSCIRC 2010 - 36th European Solid State Circuits Conference
    Pages206-209
    Number of pages4
    DOIs
    StatePublished - 27 Dec 2010
    Event36th European Solid State Circuits Conference, ESSCIRC 2010 - Sevilla, Spain
    Duration: 14 Sep 201016 Sep 2010

    Publication series

    NameESSCIRC 2010 - 36th European Solid State Circuits Conference

    Conference

    Conference36th European Solid State Circuits Conference, ESSCIRC 2010
    Country/TerritorySpain
    CitySevilla
    Period14/09/1016/09/10

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