A 50 Gb/s PAM-4 Transmitter with Feedforward Equalizer and Background Phase Error Calibration

Yu Ting Lin; Wei Zen Chen

doi:10.1109/A-SSCC48613.2020.9336134

A 50 Gb/s PAM-4 Transmitter with Feedforward Equalizer and Background Phase Error Calibration

Yu Ting Lin, Wei Zen Chen^*

^*Corresponding author for this work

Institute of Electronics

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

8 Scopus citations

Abstract

This paper presents the design of a fully integrated, 50 Gb/s PAM-4 transmitter, which consists of an on-chip pseudorandom word generator (PRWG), a 16:1 quarter-rate serializer with 4-tap FFE, and on-chip duty-cycle (DCC) and quadrature phase error calibration (QEC) loops. The dual-loop DCC and QEC can be operated concurrently on-the-fly to suppress the deterministic data jitter. Incorporating the proposed technique, the eye opening is improved by 30 %. To facilitate built-in-self-test (BIST) under high speed operation, the PRWG provides 16-path parallel test patterns, which correspond to PRBS-13Q after serializer. The experimental prototype is fabricated in a TSMC 28 nm CMOS process, and the core area is 0.214 mm2. The whole transmitter consumes 143.4 mW at 50 Gb/s operation

Original language	English
Title of host publication	2020 IEEE Asian Solid-State Circuits Conference, A-SSCC 2020
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)	9781728184364
DOIs	https://doi.org/10.1109/A-SSCC48613.2020.9336134
State	Published - 9 Nov 2020
Event	16th IEEE Asian Solid-State Circuits Conference, A-SSCC 2020 - Virtual, Hiroshima, Japan Duration: 9 Nov 2020 → 11 Nov 2020

Publication series

Name	2020 IEEE Asian Solid-State Circuits Conference, A-SSCC 2020

Conference

Conference	16th IEEE Asian Solid-State Circuits Conference, A-SSCC 2020
Country/Territory	Japan
City	Virtual, Hiroshima
Period	9/11/20 → 11/11/20

Keywords

Duty-cycle calibration (DCC)
Feedforward equalizer (FFE)
Pseudorandom word generator (PRWG)
Quadrature clock generator (QCG)
Quadrature phase error calibration(QEC)

Access to Document

10.1109/A-SSCC48613.2020.9336134

Cite this

Lin, Y. T., & Chen, W. Z. (2020). A 50 Gb/s PAM-4 Transmitter with Feedforward Equalizer and Background Phase Error Calibration. In 2020 IEEE Asian Solid-State Circuits Conference, A-SSCC 2020 Article 9336134 (2020 IEEE Asian Solid-State Circuits Conference, A-SSCC 2020). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/A-SSCC48613.2020.9336134

@inproceedings{1f5622b9b6db4abd87d73e3974c07c84,

title = "A 50 Gb/s PAM-4 Transmitter with Feedforward Equalizer and Background Phase Error Calibration",

abstract = "This paper presents the design of a fully integrated, 50 Gb/s PAM-4 transmitter, which consists of an on-chip pseudorandom word generator (PRWG), a 16:1 quarter-rate serializer with 4-tap FFE, and on-chip duty-cycle (DCC) and quadrature phase error calibration (QEC) loops. The dual-loop DCC and QEC can be operated concurrently on-the-fly to suppress the deterministic data jitter. Incorporating the proposed technique, the eye opening is improved by 30 %. To facilitate built-in-self-test (BIST) under high speed operation, the PRWG provides 16-path parallel test patterns, which correspond to PRBS-13Q after serializer. The experimental prototype is fabricated in a TSMC 28 nm CMOS process, and the core area is 0.214 mm2. The whole transmitter consumes 143.4 mW at 50 Gb/s operation ",

keywords = "Duty-cycle calibration (DCC), Feedforward equalizer (FFE), Pseudorandom word generator (PRWG), Quadrature clock generator (QCG), Quadrature phase error calibration(QEC)",

author = "Lin, {Yu Ting} and Chen, {Wei Zen}",

note = "Publisher Copyright: {\textcopyright} 2020 IEEE.; 16th IEEE Asian Solid-State Circuits Conference, A-SSCC 2020 ; Conference date: 09-11-2020 Through 11-11-2020",

year = "2020",

month = nov,

day = "9",

doi = "10.1109/A-SSCC48613.2020.9336134",

language = "English",

series = "2020 IEEE Asian Solid-State Circuits Conference, A-SSCC 2020",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

booktitle = "2020 IEEE Asian Solid-State Circuits Conference, A-SSCC 2020",

address = "美國",

}

Lin, YT & Chen, WZ 2020, A 50 Gb/s PAM-4 Transmitter with Feedforward Equalizer and Background Phase Error Calibration. in 2020 IEEE Asian Solid-State Circuits Conference, A-SSCC 2020., 9336134, 2020 IEEE Asian Solid-State Circuits Conference, A-SSCC 2020, Institute of Electrical and Electronics Engineers Inc., 16th IEEE Asian Solid-State Circuits Conference, A-SSCC 2020, Virtual, Hiroshima, Japan, 9/11/20. https://doi.org/10.1109/A-SSCC48613.2020.9336134

A 50 Gb/s PAM-4 Transmitter with Feedforward Equalizer and Background Phase Error Calibration. / Lin, Yu Ting; Chen, Wei Zen.
2020 IEEE Asian Solid-State Circuits Conference, A-SSCC 2020. Institute of Electrical and Electronics Engineers Inc., 2020. 9336134 (2020 IEEE Asian Solid-State Circuits Conference, A-SSCC 2020).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - A 50 Gb/s PAM-4 Transmitter with Feedforward Equalizer and Background Phase Error Calibration

AU - Lin, Yu Ting

AU - Chen, Wei Zen

PY - 2020/11/9

Y1 - 2020/11/9

N2 - This paper presents the design of a fully integrated, 50 Gb/s PAM-4 transmitter, which consists of an on-chip pseudorandom word generator (PRWG), a 16:1 quarter-rate serializer with 4-tap FFE, and on-chip duty-cycle (DCC) and quadrature phase error calibration (QEC) loops. The dual-loop DCC and QEC can be operated concurrently on-the-fly to suppress the deterministic data jitter. Incorporating the proposed technique, the eye opening is improved by 30 %. To facilitate built-in-self-test (BIST) under high speed operation, the PRWG provides 16-path parallel test patterns, which correspond to PRBS-13Q after serializer. The experimental prototype is fabricated in a TSMC 28 nm CMOS process, and the core area is 0.214 mm2. The whole transmitter consumes 143.4 mW at 50 Gb/s operation

AB - This paper presents the design of a fully integrated, 50 Gb/s PAM-4 transmitter, which consists of an on-chip pseudorandom word generator (PRWG), a 16:1 quarter-rate serializer with 4-tap FFE, and on-chip duty-cycle (DCC) and quadrature phase error calibration (QEC) loops. The dual-loop DCC and QEC can be operated concurrently on-the-fly to suppress the deterministic data jitter. Incorporating the proposed technique, the eye opening is improved by 30 %. To facilitate built-in-self-test (BIST) under high speed operation, the PRWG provides 16-path parallel test patterns, which correspond to PRBS-13Q after serializer. The experimental prototype is fabricated in a TSMC 28 nm CMOS process, and the core area is 0.214 mm2. The whole transmitter consumes 143.4 mW at 50 Gb/s operation

KW - Duty-cycle calibration (DCC)

KW - Feedforward equalizer (FFE)

KW - Pseudorandom word generator (PRWG)

KW - Quadrature clock generator (QCG)

KW - Quadrature phase error calibration(QEC)

UR - http://www.scopus.com/inward/record.url?scp=85100948742&partnerID=8YFLogxK

U2 - 10.1109/A-SSCC48613.2020.9336134

DO - 10.1109/A-SSCC48613.2020.9336134

M3 - Conference contribution

AN - SCOPUS:85100948742

T3 - 2020 IEEE Asian Solid-State Circuits Conference, A-SSCC 2020

BT - 2020 IEEE Asian Solid-State Circuits Conference, A-SSCC 2020

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 16th IEEE Asian Solid-State Circuits Conference, A-SSCC 2020

Y2 - 9 November 2020 through 11 November 2020

ER -

A 50 Gb/s PAM-4 Transmitter with Feedforward Equalizer and Background Phase Error Calibration

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Keywords

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