A 50 Gb/s PAM-4 Transmitter with Feedforward Equalizer and Background Phase Error Calibration

Yu Ting Lin, Wei Zen Chen*

*Corresponding author for this work

    Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

    Abstract

    This paper presents the design of a fully integrated, 50 Gb/s PAM-4 transmitter, which consists of an on-chip pseudorandom word generator (PRWG), a 16:1 quarter-rate serializer with 4-tap FFE, and on-chip duty-cycle (DCC) and quadrature phase error calibration (QEC) loops. The dual-loop DCC and QEC can be operated concurrently on-the-fly to suppress the deterministic data jitter. Incorporating the proposed technique, the eye opening is improved by 30 %. To facilitate built-in-self-test (BIST) under high speed operation, the PRWG provides 16-path parallel test patterns, which correspond to PRBS-13Q after serializer. The experimental prototype is fabricated in a TSMC 28 nm CMOS process, and the core area is 0.214 mm2. The whole transmitter consumes 143.4 mW at 50 Gb/s operation

    Original languageEnglish
    Title of host publication2020 IEEE Asian Solid-State Circuits Conference, A-SSCC 2020
    PublisherInstitute of Electrical and Electronics Engineers Inc.
    ISBN (Electronic)9781728184364
    DOIs
    StatePublished - 9 Nov 2020
    Event16th IEEE Asian Solid-State Circuits Conference, A-SSCC 2020 - Virtual, Hiroshima, Japan
    Duration: 9 Nov 202011 Nov 2020

    Publication series

    Name2020 IEEE Asian Solid-State Circuits Conference, A-SSCC 2020

    Conference

    Conference16th IEEE Asian Solid-State Circuits Conference, A-SSCC 2020
    Country/TerritoryJapan
    CityVirtual, Hiroshima
    Period9/11/2011/11/20

    Keywords

    • Duty-cycle calibration (DCC)
    • Feedforward equalizer (FFE)
    • Pseudorandom word generator (PRWG)
    • Quadrature clock generator (QCG)
    • Quadrature phase error calibration(QEC)

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