A 48 TOPS and 20943 TOPS/W 512kb Computation-in-SRAM Macro for Highly Reconfigurable Ternary CNN Acceleration

Chih Sheng Lin; Fu Cheng Tsai; Jian Wei Su; Sih Han Li; Tian-Sheuan Chang; Shyh Shyuan Sheu; Wei Chung Lo; Shih Chieh Chang; Chih I. Wu; Tuo-Hung Hou

doi:10.1109/A-SSCC53895.2021.9634797

A 48 TOPS and 20943 TOPS/W 512kb Computation-in-SRAM Macro for Highly Reconfigurable Ternary CNN Acceleration

Chih Sheng Lin, Fu Cheng Tsai, Jian Wei Su, Sih Han Li, Tian-Sheuan Chang, Shyh Shyuan Sheu, Wei Chung Lo, Shih Chieh Chang, Chih I. Wu, Tuo-Hung Hou

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

10 Scopus citations

Abstract

Energy-and area-efficient acceleration solutions are critical for the continual development of ubiquitous, real-Time, and cross-domain artificial intelligence [1]-[7]. This motivates the active research on the SRAM-based computing-in-memory (CIM) that exploits the state-of-The-Art CMOS technology and massively parallel analog computing directly inside the memory array [1]-[4]. Although significant progress has been made in recent years in improving throughput [1-2], energy efficiency [1], [3], and area efficiency [1], [4], simultaneously achieving them in SRAM-CIM remains an unsolved problem. This is particularly challenging when accounting for the potential accuracy loss due to nonideality in analog computing and the inflexibility of CIM weight-stationary designs.

Original language	English
Title of host publication	Proceedings - A-SSCC 2021
Subtitle of host publication	IEEE Asian Solid-State Circuits Conference
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)	9781665443500
DOIs	https://doi.org/10.1109/A-SSCC53895.2021.9634797
State	Published - 2021
Event	2021 IEEE Asian Solid-State Circuits Conference, A-SSCC 2021 - Busan, Korea, Republic of Duration: 7 Nov 2021 → 10 Nov 2021

Publication series

Name	Proceedings - A-SSCC 2021: IEEE Asian Solid-State Circuits Conference

Conference

Conference	2021 IEEE Asian Solid-State Circuits Conference, A-SSCC 2021
Country/Territory	Korea, Republic of
City	Busan
Period	7/11/21 → 10/11/21

UN SDGs

This output contributes to the following UN Sustainable Development Goals (SDGs)

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10.1109/A-SSCC53895.2021.9634797

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Lin, C. S., Tsai, F. C., Su, J. W., Li, S. H., Chang, T.-S., Sheu, S. S., Lo, W. C., Chang, S. C., Wu, C. I., & Hou, T.-H. (2021). A 48 TOPS and 20943 TOPS/W 512kb Computation-in-SRAM Macro for Highly Reconfigurable Ternary CNN Acceleration. In Proceedings - A-SSCC 2021: IEEE Asian Solid-State Circuits Conference (Proceedings - A-SSCC 2021: IEEE Asian Solid-State Circuits Conference). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/A-SSCC53895.2021.9634797

Lin, Chih Sheng ; Tsai, Fu Cheng ; Su, Jian Wei et al. / A 48 TOPS and 20943 TOPS/W 512kb Computation-in-SRAM Macro for Highly Reconfigurable Ternary CNN Acceleration. Proceedings - A-SSCC 2021: IEEE Asian Solid-State Circuits Conference. Institute of Electrical and Electronics Engineers Inc., 2021. (Proceedings - A-SSCC 2021: IEEE Asian Solid-State Circuits Conference).

@inproceedings{31bb303094c846cb8317f03e4d70c26c,

title = "A 48 TOPS and 20943 TOPS/W 512kb Computation-in-SRAM Macro for Highly Reconfigurable Ternary CNN Acceleration",

abstract = "Energy-and area-efficient acceleration solutions are critical for the continual development of ubiquitous, real-Time, and cross-domain artificial intelligence [1]-[7]. This motivates the active research on the SRAM-based computing-in-memory (CIM) that exploits the state-of-The-Art CMOS technology and massively parallel analog computing directly inside the memory array [1]-[4]. Although significant progress has been made in recent years in improving throughput [1-2], energy efficiency [1], [3], and area efficiency [1], [4], simultaneously achieving them in SRAM-CIM remains an unsolved problem. This is particularly challenging when accounting for the potential accuracy loss due to nonideality in analog computing and the inflexibility of CIM weight-stationary designs. ",

author = "Lin, {Chih Sheng} and Tsai, {Fu Cheng} and Su, {Jian Wei} and Li, {Sih Han} and Tian-Sheuan Chang and Sheu, {Shyh Shyuan} and Lo, {Wei Chung} and Chang, {Shih Chieh} and Wu, {Chih I.} and Tuo-Hung Hou",

note = "Publisher Copyright: {\textcopyright} 2021 IEEE.; 2021 IEEE Asian Solid-State Circuits Conference, A-SSCC 2021 ; Conference date: 07-11-2021 Through 10-11-2021",

year = "2021",

doi = "10.1109/A-SSCC53895.2021.9634797",

language = "English",

series = "Proceedings - A-SSCC 2021: IEEE Asian Solid-State Circuits Conference",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

booktitle = "Proceedings - A-SSCC 2021",

address = "美國",

}

Lin, CS, Tsai, FC, Su, JW, Li, SH, Chang, T-S, Sheu, SS, Lo, WC, Chang, SC, Wu, CI & Hou, T-H 2021, A 48 TOPS and 20943 TOPS/W 512kb Computation-in-SRAM Macro for Highly Reconfigurable Ternary CNN Acceleration. in Proceedings - A-SSCC 2021: IEEE Asian Solid-State Circuits Conference. Proceedings - A-SSCC 2021: IEEE Asian Solid-State Circuits Conference, Institute of Electrical and Electronics Engineers Inc., 2021 IEEE Asian Solid-State Circuits Conference, A-SSCC 2021, Busan, Korea, Republic of, 7/11/21. https://doi.org/10.1109/A-SSCC53895.2021.9634797

A 48 TOPS and 20943 TOPS/W 512kb Computation-in-SRAM Macro for Highly Reconfigurable Ternary CNN Acceleration. / Lin, Chih Sheng; Tsai, Fu Cheng; Su, Jian Wei et al.
Proceedings - A-SSCC 2021: IEEE Asian Solid-State Circuits Conference. Institute of Electrical and Electronics Engineers Inc., 2021. (Proceedings - A-SSCC 2021: IEEE Asian Solid-State Circuits Conference).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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AU - Lin, Chih Sheng

AU - Tsai, Fu Cheng

AU - Su, Jian Wei

AU - Li, Sih Han

AU - Chang, Tian-Sheuan

AU - Sheu, Shyh Shyuan

AU - Lo, Wei Chung

AU - Chang, Shih Chieh

AU - Wu, Chih I.

AU - Hou, Tuo-Hung

PY - 2021

Y1 - 2021

N2 - Energy-and area-efficient acceleration solutions are critical for the continual development of ubiquitous, real-Time, and cross-domain artificial intelligence [1]-[7]. This motivates the active research on the SRAM-based computing-in-memory (CIM) that exploits the state-of-The-Art CMOS technology and massively parallel analog computing directly inside the memory array [1]-[4]. Although significant progress has been made in recent years in improving throughput [1-2], energy efficiency [1], [3], and area efficiency [1], [4], simultaneously achieving them in SRAM-CIM remains an unsolved problem. This is particularly challenging when accounting for the potential accuracy loss due to nonideality in analog computing and the inflexibility of CIM weight-stationary designs.

AB - Energy-and area-efficient acceleration solutions are critical for the continual development of ubiquitous, real-Time, and cross-domain artificial intelligence [1]-[7]. This motivates the active research on the SRAM-based computing-in-memory (CIM) that exploits the state-of-The-Art CMOS technology and massively parallel analog computing directly inside the memory array [1]-[4]. Although significant progress has been made in recent years in improving throughput [1-2], energy efficiency [1], [3], and area efficiency [1], [4], simultaneously achieving them in SRAM-CIM remains an unsolved problem. This is particularly challenging when accounting for the potential accuracy loss due to nonideality in analog computing and the inflexibility of CIM weight-stationary designs.

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M3 - Conference contribution

AN - SCOPUS:85124041212

T3 - Proceedings - A-SSCC 2021: IEEE Asian Solid-State Circuits Conference

BT - Proceedings - A-SSCC 2021

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 2021 IEEE Asian Solid-State Circuits Conference, A-SSCC 2021

Y2 - 7 November 2021 through 10 November 2021

ER -

Lin CS, Tsai FC, Su JW, Li SH, Chang TS, Sheu SS et al. A 48 TOPS and 20943 TOPS/W 512kb Computation-in-SRAM Macro for Highly Reconfigurable Ternary CNN Acceleration. In Proceedings - A-SSCC 2021: IEEE Asian Solid-State Circuits Conference. Institute of Electrical and Electronics Engineers Inc. 2021. (Proceedings - A-SSCC 2021: IEEE Asian Solid-State Circuits Conference). doi: 10.1109/A-SSCC53895.2021.9634797

A 48 TOPS and 20943 TOPS/W 512kb Computation-in-SRAM Macro for Highly Reconfigurable Ternary CNN Acceleration

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