A 48 TOPS and 20943 TOPS/W 512kb Computation-in-SRAM Macro for Highly Reconfigurable Ternary CNN Acceleration

Chih Sheng Lin, Fu Cheng Tsai, Jian Wei Su, Sih Han Li, Tian-Sheuan Chang, Shyh Shyuan Sheu, Wei Chung Lo, Shih Chieh Chang, Chih I. Wu, Tuo-Hung Hou

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

1 Scopus citations

Abstract

Energy-and area-efficient acceleration solutions are critical for the continual development of ubiquitous, real-Time, and cross-domain artificial intelligence [1]-[7]. This motivates the active research on the SRAM-based computing-in-memory (CIM) that exploits the state-of-The-Art CMOS technology and massively parallel analog computing directly inside the memory array [1]-[4]. Although significant progress has been made in recent years in improving throughput [1-2], energy efficiency [1], [3], and area efficiency [1], [4], simultaneously achieving them in SRAM-CIM remains an unsolved problem. This is particularly challenging when accounting for the potential accuracy loss due to nonideality in analog computing and the inflexibility of CIM weight-stationary designs.

Original languageEnglish
Title of host publicationProceedings - A-SSCC 2021
Subtitle of host publicationIEEE Asian Solid-State Circuits Conference
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9781665443500
DOIs
StatePublished - 2021
Event2021 IEEE Asian Solid-State Circuits Conference, A-SSCC 2021 - Busan, Korea, Republic of
Duration: 7 Nov 202110 Nov 2021

Publication series

NameProceedings - A-SSCC 2021: IEEE Asian Solid-State Circuits Conference

Conference

Conference2021 IEEE Asian Solid-State Circuits Conference, A-SSCC 2021
Country/TerritoryKorea, Republic of
CityBusan
Period7/11/2110/11/21

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