TY - GEN
T1 - A 45nm 6b/cell charge-trapping flash memory using LDPC-based ECC and drift-immune soft-sensing engine
AU - Ho, Kin Chu
AU - Fang, Po Chao
AU - Li, Hsiang Pang
AU - Wang, Cheng Yuan Michael
AU - Chang, Hsie-Chia
PY - 2013/4/29
Y1 - 2013/4/29
N2 - To satisfy the demand of higher storage density, storing multiple-bits-per-cell technique is widely adopted. As presented in [1], a 4b/cell Flash memory by using error-detection (ED) scheme stores 2b data on two sides of a memory cell individually. Since the noise margin becomes smaller, the distribution drifts due to program disturb, data retention and temperature variation will cause higher raw bit-error-rate (RBER) if the sensing level (voltage) are not adjusted accordingly. The ED scheme can detect the drift direction by counting and storing the number of cells (Ni) with threshold voltage (VTH) below the ith sensing level (V REF i). A simple example with page size 1KB is demonstrated in Fig. 12.7.1. During a read operation, the number of cells (Ni, measured) whose VTH below VREF i is counted and compared to N i. The ED scheme can find out a sub-optimal sensing level when N i, measured and Ni is close enough. In this paper, a production 16Gb 45nm 4b/cell ONO-based charge-trapping (CT) Flash memory is demonstrated to achieve 6b/cell capability. Since the adjacent distributions for 6b/cell are much closer to each other, even a BCH code with ED scheme fails to correct all the patterns. However, by using a new 1-3-3 mapping and LDPC codes with a developed drift-immune soft-sensing (DI-SS) engine, the 45nm 4b/cell CT Flash memory is boosted to 6b/cell. The data flow of programming data is also shown in Fig. 12.7.1.
AB - To satisfy the demand of higher storage density, storing multiple-bits-per-cell technique is widely adopted. As presented in [1], a 4b/cell Flash memory by using error-detection (ED) scheme stores 2b data on two sides of a memory cell individually. Since the noise margin becomes smaller, the distribution drifts due to program disturb, data retention and temperature variation will cause higher raw bit-error-rate (RBER) if the sensing level (voltage) are not adjusted accordingly. The ED scheme can detect the drift direction by counting and storing the number of cells (Ni) with threshold voltage (VTH) below the ith sensing level (V REF i). A simple example with page size 1KB is demonstrated in Fig. 12.7.1. During a read operation, the number of cells (Ni, measured) whose VTH below VREF i is counted and compared to N i. The ED scheme can find out a sub-optimal sensing level when N i, measured and Ni is close enough. In this paper, a production 16Gb 45nm 4b/cell ONO-based charge-trapping (CT) Flash memory is demonstrated to achieve 6b/cell capability. Since the adjacent distributions for 6b/cell are much closer to each other, even a BCH code with ED scheme fails to correct all the patterns. However, by using a new 1-3-3 mapping and LDPC codes with a developed drift-immune soft-sensing (DI-SS) engine, the 45nm 4b/cell CT Flash memory is boosted to 6b/cell. The data flow of programming data is also shown in Fig. 12.7.1.
UR - http://www.scopus.com/inward/record.url?scp=84876585755&partnerID=8YFLogxK
U2 - 10.1109/ISSCC.2013.6487709
DO - 10.1109/ISSCC.2013.6487709
M3 - Conference contribution
AN - SCOPUS:84876585755
SN - 9781467345132
T3 - Digest of Technical Papers - IEEE International Solid-State Circuits Conference
SP - 222
EP - 223
BT - 2013 IEEE International Solid-State Circuits Conference, ISSCC 2013 - Digest of Technical Papers
T2 - 2013 60th IEEE International Solid-State Circuits Conference, ISSCC 2013
Y2 - 17 February 2013 through 21 February 2013
ER -