TY - JOUR
T1 - A 44.3-mW 62.4-fps Hyperspectral Image Processor for Spectral Unmixing in MAV Remote Sensing
AU - Lo, Yu Chen
AU - Wu, Yi Chung
AU - Yang, Chia Hsiang
N1 - Publisher Copyright:
© 2024 IEEE.
PY - 2024
Y1 - 2024
N2 - This article presents the first dedicated processor designed to support the complete spectral unmixing workflow for hyperspectral image (HSI) processing, including rank reduction, endmember extraction, and abundance estimation. The design employs architecture explorations, including folding and data interleaving, to reduce hardware complexity. To enhance the throughput, the processor incorporates deeply pipelined reconfigurable processing elements (PEs) for compute-intensive tasks involved in spectral unmixing. The proposed sparsity-adaptive clocking technique leverages data sparsity and minimizes dynamic power consumption. Fabricated in a 40-nm CMOS technology, the proposed processor occupies a core area of 2.56 mm2. The chip consumes 44.3 mW of power at a clock frequency of 175 MHz from a 0.68-V supply. The processor can concurrently generate eight endmembers and their associated abundances for a 256 × 256 × 64 HSI, resulting in a throughput of 62.4 fps. Comparative analysis with a high-end CPU demonstrates a significant processing speed improvement of 544× , accompanied by energy efficiency that is 1 735 537× higher and area efficiency that is 31 647× higher. The proposed processor is 17.5× faster, with 236 735× higher energy efficiency and 4158× higher area efficiency in comparison to a high-end graphics processing unit (GPU). The proposed processor provides a promising solution to support real-time hyperspectral remote sensing, particularly for battery-powered micro air vehicles (MAVs).
AB - This article presents the first dedicated processor designed to support the complete spectral unmixing workflow for hyperspectral image (HSI) processing, including rank reduction, endmember extraction, and abundance estimation. The design employs architecture explorations, including folding and data interleaving, to reduce hardware complexity. To enhance the throughput, the processor incorporates deeply pipelined reconfigurable processing elements (PEs) for compute-intensive tasks involved in spectral unmixing. The proposed sparsity-adaptive clocking technique leverages data sparsity and minimizes dynamic power consumption. Fabricated in a 40-nm CMOS technology, the proposed processor occupies a core area of 2.56 mm2. The chip consumes 44.3 mW of power at a clock frequency of 175 MHz from a 0.68-V supply. The processor can concurrently generate eight endmembers and their associated abundances for a 256 × 256 × 64 HSI, resulting in a throughput of 62.4 fps. Comparative analysis with a high-end CPU demonstrates a significant processing speed improvement of 544× , accompanied by energy efficiency that is 1 735 537× higher and area efficiency that is 31 647× higher. The proposed processor is 17.5× faster, with 236 735× higher energy efficiency and 4158× higher area efficiency in comparison to a high-end graphics processing unit (GPU). The proposed processor provides a promising solution to support real-time hyperspectral remote sensing, particularly for battery-powered micro air vehicles (MAVs).
KW - CMOS integrated circuits
KW - domain-specific processor
KW - energy-efficient architecture
KW - hyperspectral imaging
KW - spectral unmixing
UR - http://www.scopus.com/inward/record.url?scp=85204706616&partnerID=8YFLogxK
U2 - 10.1109/JSSC.2024.3456889
DO - 10.1109/JSSC.2024.3456889
M3 - Article
AN - SCOPUS:85204706616
SN - 0018-9200
JO - IEEE Journal of Solid-State Circuits
JF - IEEE Journal of Solid-State Circuits
ER -