A 44.3-mW 62.4-fps Hyperspectral Image Processor for Spectral Unmixing in MAV Remote Sensing

Yu Chen Lo, Yi Chung Wu, Chia Hsiang Yang*

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

Abstract

This article presents the first dedicated processor designed to support the complete spectral unmixing workflow for hyperspectral image (HSI) processing, including rank reduction, endmember extraction, and abundance estimation. The design employs architecture explorations, including folding and data interleaving, to reduce hardware complexity. To enhance the throughput, the processor incorporates deeply pipelined reconfigurable processing elements (PEs) for compute-intensive tasks involved in spectral unmixing. The proposed sparsity-adaptive clocking technique leverages data sparsity and minimizes dynamic power consumption. Fabricated in a 40-nm CMOS technology, the proposed processor occupies a core area of 2.56 mm2. The chip consumes 44.3 mW of power at a clock frequency of 175 MHz from a 0.68-V supply. The processor can concurrently generate eight endmembers and their associated abundances for a 256 × 256 × 64 HSI, resulting in a throughput of 62.4 fps. Comparative analysis with a high-end CPU demonstrates a significant processing speed improvement of 544× , accompanied by energy efficiency that is 1 735 537× higher and area efficiency that is 31 647× higher. The proposed processor is 17.5× faster, with 236 735× higher energy efficiency and 4158× higher area efficiency in comparison to a high-end graphics processing unit (GPU). The proposed processor provides a promising solution to support real-time hyperspectral remote sensing, particularly for battery-powered micro air vehicles (MAVs).

Original languageEnglish
JournalIEEE Journal of Solid-State Circuits
DOIs
StateAccepted/In press - 2024

Keywords

  • CMOS integrated circuits
  • domain-specific processor
  • energy-efficient architecture
  • hyperspectral imaging
  • spectral unmixing

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