A 4.2 nW and 18 ppm/°C temperature coefficient leakage-based square root compensation (LSRC) CMOS voltage reference

Chao Jen Huang; Yan Jiun Lai; Yu Jheng Ou Yang; Hung Wei Chen; Chun Chieh Kuo; Ke-Horng Chen; Ying Hsi Lin; Shian Ru Lin; Tsung Yen Tsai

doi:10.1109/TCSII.2019.2908284

A 4.2 nW and 18 ppm/°C temperature coefficient leakage-based square root compensation (LSRC) CMOS voltage reference

Chao Jen Huang, Yan Jiun Lai, Yu Jheng Ou Yang, Hung Wei Chen, Chun Chieh Kuo, Ke-Horng Chen^*, Ying Hsi Lin, Shian Ru Lin, Tsung Yen Tsai

^*Corresponding author for this work

Department of Electrical and Computer Engineering

Research output: Contribution to journal › Article › peer-review

12 Scopus citations

Abstract

State-of-the-art CMOS-based voltage reference suffer from a trade-off between power dissipation and temperature coefficient (TC) due to the limited order of compensation in an advanced process which features a low supplied voltage (11.2 V). The proposed voltage reference with leakage-based square root compensation (LSRC) technique bias the substrate to offset TC with ultra-low leakage current (100300 pA). On the other hand, the architecture provides an extensible order of compensation which is independent of voltage headroom. The two LSRC branches voltage reference implemented in 40 nm CMOS process achieves a within-wafer σ/μ of 0.204 and a TC of 18 ppm/°C with a power consumption of 4.2 nW.

Original language	English
Article number	8676347
Pages (from-to)	728-732
Number of pages	5
Journal	IEEE Transactions on Circuits and Systems I: Regular Papers
Volume	66
Issue number	5
DOIs	https://doi.org/10.1109/TCSII.2019.2908284
State	Published - 1 May 2019

Keywords

Temperature coefficient (TC) compensation
leakage-based square root compensation (LSRC) technique
low power consumption

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Huang, C. J., Lai, Y. J., Yang, Y. J. O., Chen, H. W., Kuo, C. C., Chen, K.-H., Lin, Y. H., Lin, S. R., & Tsai, T. Y. (2019). A 4.2 nW and 18 ppm/°C temperature coefficient leakage-based square root compensation (LSRC) CMOS voltage reference. IEEE Transactions on Circuits and Systems I: Regular Papers, 66(5), 728-732. Article 8676347. https://doi.org/10.1109/TCSII.2019.2908284

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title = "A 4.2 nW and 18 ppm/°C temperature coefficient leakage-based square root compensation (LSRC) CMOS voltage reference",

abstract = "State-of-the-art CMOS-based voltage reference suffer from a trade-off between power dissipation and temperature coefficient (TC) due to the limited order of compensation in an advanced process which features a low supplied voltage (11.2 V). The proposed voltage reference with leakage-based square root compensation (LSRC) technique bias the substrate to offset TC with ultra-low leakage current (100300 pA). On the other hand, the architecture provides an extensible order of compensation which is independent of voltage headroom. The two LSRC branches voltage reference implemented in 40 nm CMOS process achieves a within-wafer σ/μ of 0.204 and a TC of 18 ppm/°C with a power consumption of 4.2 nW.",

keywords = "Temperature coefficient (TC) compensation, leakage-based square root compensation (LSRC) technique, low power consumption",

author = "Huang, {Chao Jen} and Lai, {Yan Jiun} and Yang, {Yu Jheng Ou} and Chen, {Hung Wei} and Kuo, {Chun Chieh} and Ke-Horng Chen and Lin, {Ying Hsi} and Lin, {Shian Ru} and Tsai, {Tsung Yen}",

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T1 - A 4.2 nW and 18 ppm/°C temperature coefficient leakage-based square root compensation (LSRC) CMOS voltage reference

AU - Huang, Chao Jen

AU - Lai, Yan Jiun

AU - Yang, Yu Jheng Ou

AU - Chen, Hung Wei

AU - Kuo, Chun Chieh

AU - Chen, Ke-Horng

AU - Lin, Ying Hsi

AU - Lin, Shian Ru

AU - Tsai, Tsung Yen

PY - 2019/5/1

Y1 - 2019/5/1

N2 - State-of-the-art CMOS-based voltage reference suffer from a trade-off between power dissipation and temperature coefficient (TC) due to the limited order of compensation in an advanced process which features a low supplied voltage (11.2 V). The proposed voltage reference with leakage-based square root compensation (LSRC) technique bias the substrate to offset TC with ultra-low leakage current (100300 pA). On the other hand, the architecture provides an extensible order of compensation which is independent of voltage headroom. The two LSRC branches voltage reference implemented in 40 nm CMOS process achieves a within-wafer σ/μ of 0.204 and a TC of 18 ppm/°C with a power consumption of 4.2 nW.

AB - State-of-the-art CMOS-based voltage reference suffer from a trade-off between power dissipation and temperature coefficient (TC) due to the limited order of compensation in an advanced process which features a low supplied voltage (11.2 V). The proposed voltage reference with leakage-based square root compensation (LSRC) technique bias the substrate to offset TC with ultra-low leakage current (100300 pA). On the other hand, the architecture provides an extensible order of compensation which is independent of voltage headroom. The two LSRC branches voltage reference implemented in 40 nm CMOS process achieves a within-wafer σ/μ of 0.204 and a TC of 18 ppm/°C with a power consumption of 4.2 nW.

KW - Temperature coefficient (TC) compensation

KW - leakage-based square root compensation (LSRC) technique

KW - low power consumption

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A 4.2 nW and 18 ppm/°C temperature coefficient leakage-based square root compensation (LSRC) CMOS voltage reference

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Keywords

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