A 40nm 1.0Mb 6T pipeline SRAM with digital-based Bit-Line Under-Drive, Three-Step-Up Word-Line, Adaptive Data-Aware Write-Assist with VCS tracking and Adaptive Voltage Detector for boosting control

Wei Nan Liao; Nan Chun Lien; Chi Shin Chang; Li Wei Chu; Hao I. Yang; Ching Te Chuang; Shyh-Jye Jou; Wei Hwang; Ming Hsien Tu; Huan Shun Huang; Jian Hao Wang; Paul Sen Kan; Yong Jyun Hu

doi:10.1109/SOCC.2013.6749670

A 40nm 1.0Mb 6T pipeline SRAM with digital-based Bit-Line Under-Drive, Three-Step-Up Word-Line, Adaptive Data-Aware Write-Assist with VCS tracking and Adaptive Voltage Detector for boosting control

Wei Nan Liao, Nan Chun Lien, Chi Shin Chang, Li Wei Chu, Hao I. Yang, Ching Te Chuang, Shyh-Jye Jou, Wei Hwang, Ming Hsien Tu, Huan Shun Huang, Jian Hao Wang, Paul Sen Kan, Yong Jyun Hu

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

1 Scopus citations

Abstract

This paper presents a 40nm 1.0Mb pipeline 6T SRAM featuring digital-based Bit-Line Under-Drive (BLUD) with large-signal sensing and Three-Step-Up Word-Line (TSUWL) to improve RSNM, Read performance and Write-ability. An Adaptive Data-Aware Write-Assist (ADAWA) with VCS tracking is employed to further improve Write-ability while ensuring adequate stability for half-selected cells on the selected bit-lines. An Adaptive Voltage Detector (AVD) with binary boosting control is used to mitigate gate dielectric over-stress. The 1.0Mb test chip operates from 1.5V to 0.7V, with operating frequency of [email protected] and [email protected] at 25°C. The measured power consumption is 43.47mW (Active)/3.91mW (Leakage) at 1.1V and 8.97mW (Active)/0.52mW (Leakage) at 0.7V, TT, 25°C.

Original language	English
Title of host publication	Proceedings - IEEE 26th International SOC Conference, SOCC 2013
Publisher	IEEE Computer Society
Pages	110-115
Number of pages	6
ISBN (Print)	9781479911660
DOIs	https://doi.org/10.1109/SOCC.2013.6749670
State	Published - 1 Jan 2013
Event	26th IEEE International System-on-Chip Conference, SOCC 2013 - Erlangen, Germany Duration: 4 Sep 2013 → 6 Sep 2013

Publication series

Name	International System on Chip Conference
ISSN (Print)	2164-1676
ISSN (Electronic)	2164-1706

Conference

Conference	26th IEEE International System-on-Chip Conference, SOCC 2013
Country/Territory	Germany
City	Erlangen
Period	4/09/13 → 6/09/13

Access to Document

10.1109/SOCC.2013.6749670

Cite this

Liao, W. N., Lien, N. C., Chang, C. S., Chu, L. W., Yang, H. I., Chuang, C. T., Jou, S.-J., Hwang, W., Tu, M. H., Huang, H. S., Wang, J. H., Kan, P. S., & Hu, Y. J. (2013). A 40nm 1.0Mb 6T pipeline SRAM with digital-based Bit-Line Under-Drive, Three-Step-Up Word-Line, Adaptive Data-Aware Write-Assist with VCS tracking and Adaptive Voltage Detector for boosting control. In Proceedings - IEEE 26th International SOC Conference, SOCC 2013 (pp. 110-115). Article 6749670 (International System on Chip Conference). IEEE Computer Society. https://doi.org/10.1109/SOCC.2013.6749670

Liao, Wei Nan ; Lien, Nan Chun ; Chang, Chi Shin et al. / A 40nm 1.0Mb 6T pipeline SRAM with digital-based Bit-Line Under-Drive, Three-Step-Up Word-Line, Adaptive Data-Aware Write-Assist with VCS tracking and Adaptive Voltage Detector for boosting control. Proceedings - IEEE 26th International SOC Conference, SOCC 2013. IEEE Computer Society, 2013. pp. 110-115 (International System on Chip Conference).

@inproceedings{022ded0df5a84d8aa0afd10a1444ef46,

title = "A 40nm 1.0Mb 6T pipeline SRAM with digital-based Bit-Line Under-Drive, Three-Step-Up Word-Line, Adaptive Data-Aware Write-Assist with VCS tracking and Adaptive Voltage Detector for boosting control",

abstract = "This paper presents a 40nm 1.0Mb pipeline 6T SRAM featuring digital-based Bit-Line Under-Drive (BLUD) with large-signal sensing and Three-Step-Up Word-Line (TSUWL) to improve RSNM, Read performance and Write-ability. An Adaptive Data-Aware Write-Assist (ADAWA) with VCS tracking is employed to further improve Write-ability while ensuring adequate stability for half-selected cells on the selected bit-lines. An Adaptive Voltage Detector (AVD) with binary boosting control is used to mitigate gate dielectric over-stress. The 1.0Mb test chip operates from 1.5V to 0.7V, with operating frequency of [email protected] and [email protected] at 25°C. The measured power consumption is 43.47mW (Active)/3.91mW (Leakage) at 1.1V and 8.97mW (Active)/0.52mW (Leakage) at 0.7V, TT, 25°C.",

author = "Liao, \{Wei Nan\} and Lien, \{Nan Chun\} and Chang, \{Chi Shin\} and Chu, \{Li Wei\} and Yang, \{Hao I.\} and Chuang, \{Ching Te\} and Shyh-Jye Jou and Wei Hwang and Tu, \{Ming Hsien\} and Huang, \{Huan Shun\} and Wang, \{Jian Hao\} and Kan, \{Paul Sen\} and Hu, \{Yong Jyun\}",

year = "2013",

month = jan,

day = "1",

doi = "10.1109/SOCC.2013.6749670",

language = "English",

isbn = "9781479911660",

series = "International System on Chip Conference",

publisher = "IEEE Computer Society",

pages = "110--115",

booktitle = "Proceedings - IEEE 26th International SOC Conference, SOCC 2013",

address = "美國",

note = "26th IEEE International System-on-Chip Conference, SOCC 2013 ; Conference date: 04-09-2013 Through 06-09-2013",

}

Liao, WN, Lien, NC, Chang, CS, Chu, LW, Yang, HI, Chuang, CT, Jou, S-J, Hwang, W, Tu, MH, Huang, HS, Wang, JH, Kan, PS & Hu, YJ 2013, A 40nm 1.0Mb 6T pipeline SRAM with digital-based Bit-Line Under-Drive, Three-Step-Up Word-Line, Adaptive Data-Aware Write-Assist with VCS tracking and Adaptive Voltage Detector for boosting control. in Proceedings - IEEE 26th International SOC Conference, SOCC 2013., 6749670, International System on Chip Conference, IEEE Computer Society, pp. 110-115, 26th IEEE International System-on-Chip Conference, SOCC 2013, Erlangen, Germany, 4/09/13. https://doi.org/10.1109/SOCC.2013.6749670

A 40nm 1.0Mb 6T pipeline SRAM with digital-based Bit-Line Under-Drive, Three-Step-Up Word-Line, Adaptive Data-Aware Write-Assist with VCS tracking and Adaptive Voltage Detector for boosting control. / Liao, Wei Nan; Lien, Nan Chun; Chang, Chi Shin et al.
Proceedings - IEEE 26th International SOC Conference, SOCC 2013. IEEE Computer Society, 2013. p. 110-115 6749670 (International System on Chip Conference).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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AU - Liao, Wei Nan

AU - Lien, Nan Chun

AU - Chang, Chi Shin

AU - Chu, Li Wei

AU - Yang, Hao I.

AU - Chuang, Ching Te

AU - Jou, Shyh-Jye

AU - Hwang, Wei

AU - Tu, Ming Hsien

AU - Huang, Huan Shun

AU - Wang, Jian Hao

AU - Kan, Paul Sen

AU - Hu, Yong Jyun

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N2 - This paper presents a 40nm 1.0Mb pipeline 6T SRAM featuring digital-based Bit-Line Under-Drive (BLUD) with large-signal sensing and Three-Step-Up Word-Line (TSUWL) to improve RSNM, Read performance and Write-ability. An Adaptive Data-Aware Write-Assist (ADAWA) with VCS tracking is employed to further improve Write-ability while ensuring adequate stability for half-selected cells on the selected bit-lines. An Adaptive Voltage Detector (AVD) with binary boosting control is used to mitigate gate dielectric over-stress. The 1.0Mb test chip operates from 1.5V to 0.7V, with operating frequency of [email protected] and [email protected] at 25°C. The measured power consumption is 43.47mW (Active)/3.91mW (Leakage) at 1.1V and 8.97mW (Active)/0.52mW (Leakage) at 0.7V, TT, 25°C.

AB - This paper presents a 40nm 1.0Mb pipeline 6T SRAM featuring digital-based Bit-Line Under-Drive (BLUD) with large-signal sensing and Three-Step-Up Word-Line (TSUWL) to improve RSNM, Read performance and Write-ability. An Adaptive Data-Aware Write-Assist (ADAWA) with VCS tracking is employed to further improve Write-ability while ensuring adequate stability for half-selected cells on the selected bit-lines. An Adaptive Voltage Detector (AVD) with binary boosting control is used to mitigate gate dielectric over-stress. The 1.0Mb test chip operates from 1.5V to 0.7V, with operating frequency of [email protected] and [email protected] at 25°C. The measured power consumption is 43.47mW (Active)/3.91mW (Leakage) at 1.1V and 8.97mW (Active)/0.52mW (Leakage) at 0.7V, TT, 25°C.

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DO - 10.1109/SOCC.2013.6749670

M3 - Conference contribution

AN - SCOPUS:84898436701

SN - 9781479911660

T3 - International System on Chip Conference

SP - 110

EP - 115

BT - Proceedings - IEEE 26th International SOC Conference, SOCC 2013

PB - IEEE Computer Society

T2 - 26th IEEE International System-on-Chip Conference, SOCC 2013

Y2 - 4 September 2013 through 6 September 2013

ER -

Liao WN, Lien NC, Chang CS, Chu LW, Yang HI, Chuang CT et al. A 40nm 1.0Mb 6T pipeline SRAM with digital-based Bit-Line Under-Drive, Three-Step-Up Word-Line, Adaptive Data-Aware Write-Assist with VCS tracking and Adaptive Voltage Detector for boosting control. In Proceedings - IEEE 26th International SOC Conference, SOCC 2013. IEEE Computer Society. 2013. p. 110-115. 6749670. (International System on Chip Conference). doi: 10.1109/SOCC.2013.6749670

A 40nm 1.0Mb 6T pipeline SRAM with digital-based Bit-Line Under-Drive, Three-Step-Up Word-Line, Adaptive Data-Aware Write-Assist with VCS tracking and Adaptive Voltage Detector for boosting control

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