A 4-Mbit NAND-EEPROM with tight programmed Vt distribution

Tomoharu Tanaka; Masaki Momodomi; Yoshihisa Iwata; Yoshiyuki Tanaka; Hideko Oodaira; Yasuo Itoh; Shirota Riichiro; Kazunori Ohuchi; Fujio Masuoka

doi:10.1109/VLSIC.1990.111117

A 4-Mbit NAND-EEPROM with tight programmed V_t distribution

Tomoharu Tanaka^*, Masaki Momodomi, Yoshihisa Iwata, Yoshiyuki Tanaka, Hideko Oodaira, Yasuo Itoh, Shirota Riichiro, Kazunori Ohuchi, Fujio Masuoka

^*Corresponding author for this work

Department of Electrical and Computer Engineering

Research output: Contribution to conference › Paper › peer-review

15 Scopus citations

Abstract

The authors describe a 4-Mb NAND-EEPROM with tight V_t (threshold voltage) distribution which is controlled by a novel program verify technique. A tight V_t distribution width of 0.6 V for the entire 4-Mb cell array is achieved, and read margin is improved. A unique twin P-well structure has made it possible to realize low-power 5-V-only erase/program operation easily compared with the previous design.

Original language	English
Pages	105-106
Number of pages	2
DOIs	https://doi.org/10.1109/VLSIC.1990.111117
State	Published - Jun 1990
Event	1990 Symposium on VLSI Circuits - Honolulu, HI, USA Duration: 7 Jun 1990 → 9 Jun 1990

Conference

Conference	1990 Symposium on VLSI Circuits
City	Honolulu, HI, USA
Period	7/06/90 → 9/06/90

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10.1109/VLSIC.1990.111117

Cite this

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abstract = "The authors describe a 4-Mb NAND-EEPROM with tight Vt (threshold voltage) distribution which is controlled by a novel program verify technique. A tight Vt distribution width of 0.6 V for the entire 4-Mb cell array is achieved, and read margin is improved. A unique twin P-well structure has made it possible to realize low-power 5-V-only erase/program operation easily compared with the previous design.",

author = "Tomoharu Tanaka and Masaki Momodomi and Yoshihisa Iwata and Yoshiyuki Tanaka and Hideko Oodaira and Yasuo Itoh and Shirota Riichiro and Kazunori Ohuchi and Fujio Masuoka",

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doi = "10.1109/VLSIC.1990.111117",

language = "English",

pages = "105--106",

note = "1990 Symposium on VLSI Circuits ; Conference date: 07-06-1990 Through 09-06-1990",

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AU - Tanaka, Tomoharu

AU - Momodomi, Masaki

AU - Iwata, Yoshihisa

AU - Tanaka, Yoshiyuki

AU - Oodaira, Hideko

AU - Itoh, Yasuo

AU - Riichiro, Shirota

AU - Ohuchi, Kazunori

AU - Masuoka, Fujio

PY - 1990/6

Y1 - 1990/6

N2 - The authors describe a 4-Mb NAND-EEPROM with tight Vt (threshold voltage) distribution which is controlled by a novel program verify technique. A tight Vt distribution width of 0.6 V for the entire 4-Mb cell array is achieved, and read margin is improved. A unique twin P-well structure has made it possible to realize low-power 5-V-only erase/program operation easily compared with the previous design.

AB - The authors describe a 4-Mb NAND-EEPROM with tight Vt (threshold voltage) distribution which is controlled by a novel program verify technique. A tight Vt distribution width of 0.6 V for the entire 4-Mb cell array is achieved, and read margin is improved. A unique twin P-well structure has made it possible to realize low-power 5-V-only erase/program operation easily compared with the previous design.

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U2 - 10.1109/VLSIC.1990.111117

DO - 10.1109/VLSIC.1990.111117

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T2 - 1990 Symposium on VLSI Circuits

Y2 - 7 June 1990 through 9 June 1990

ER -

A 4-Mbit NAND-EEPROM with tight programmed V_t distribution

Abstract

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