@inproceedings{0e4d19994367414384702edcc176c991,
title = "A 38mW 40Gb/s 4-lane tri-band PAM-4 / 16-QAM transceiver in 28nm CMOS for high-speed Memory interface",
abstract = "The continuous scaling of CMOS technology increases processor performance and memory capacity, requiring the CPU/Memory interface to have ever-higher bandwidth and energy efficiency over the past few years. Among those cutting-edge interface technologies, multi-band (multi-tone) signaling has shown great potential because of its high data-rate capability along with its low energy consumption [3]-[5]. With spectrally divided signaling, the multi-band transceiver can be designed to avoid spectral notches with extended communication bandwidth of multi-drop buses [4]. Also, its unique self-equalized double-sideband signaling renders the multi-band transceiver immune to inter-symbol interference caused by channel attenuation without additional equalization circuitry [5]. To further improve the capability and validate the scalability of multi-band signaling, we have realized a tri-band transceiver with four parallel lanes and achieved a total data rate of 40Gb/s, with total power consumption of 38mW in 28nm CMOS technology.",
author = "Cho, {Wei Han} and Yilei Li and Yuan Du and Wong, {Chien Heng} and Jieqiong Du and Po-Tsang Huang and Lee, {Sheau Jiung} and Chen, {Huan Neng} and Jou, {Chewn Pu} and Hsueh, {Fu Lung} and Mau-Chung Chang",
year = "2016",
month = feb,
day = "23",
doi = "10.1109/ISSCC.2016.7417968",
language = "English",
series = "Digest of Technical Papers - IEEE International Solid-State Circuits Conference",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
pages = "184--185",
booktitle = "2016 IEEE International Solid-State Circuits Conference, ISSCC 2016",
address = "United States",
note = "63rd IEEE International Solid-State Circuits Conference, ISSCC 2016 ; Conference date: 31-01-2016 Through 04-02-2016",
}
