A 38.64-Gb/s Large-CPM 2-KB LDPC Decoder Implementation for nand Flash Memories

Li Wei Liu; MU-HUA YUAN; Yen Chin Liao; Hsie-Chia Chang

doi:10.1109/OJCAS.2022.3203849

A 38.64-Gb/s Large-CPM 2-KB LDPC Decoder Implementation for nand Flash Memories

Li Wei Liu^*, MU-HUA YUAN, Yen Chin Liao, Hsie-Chia Chang

^*Corresponding author for this work

Institute of Electronics

Research output: Contribution to journal › Article › peer-review

5 Scopus citations

Abstract

The routing congestion over a QC-LDPC decoder with a large circular permutation matrix (CPM) size has long been an obstacle to high throughput designs. This paper presents a large-CPM congestion-free decoder for (18396, 16416) quasi-cyclic Euclidean geometry low-density parity-check (QC-EG-LDPC) code in NAND flash application. Considering area efficiency in scheduling schemes and the array dispersion structure, the Array-Disperse Based Dual Variable Node Unit (VNU) Cluster Architecture fully leverages the code structure to support at least two physical channels of the Open NAND Flash Interface 5.0 (ONFI 5.0). In addition, the proposed congestion-aware analysis and implementation method achieve a highly parallel decoder at a 70% utilization ratio. Implemented in TSMC 28nm process, the presented decoder provides 38.64 Gbps throughput at RBER=1.456% Bi-AWGN channel with an area of 2.97 mm2.

Original language	American English
Pages (from-to)	180-191
Journal	IEEE Open Journal of Circuits and Systems
Volume	3
DOIs	https://doi.org/10.1109/OJCAS.2022.3203849
State	Published - 1 Sep 2022

Access to Document

10.1109/OJCAS.2022.3203849

Cite this

@article{201df761ebf54ca68325f73dd29d2f07,

title = "A 38.64-Gb/s Large-CPM 2-KB LDPC Decoder Implementation for nand Flash Memories",

abstract = "The routing congestion over a QC-LDPC decoder with a large circular permutation matrix (CPM) size has long been an obstacle to high throughput designs. This paper presents a large-CPM congestion-free decoder for (18396, 16416) quasi-cyclic Euclidean geometry low-density parity-check (QC-EG-LDPC) code in NAND flash application. Considering area efficiency in scheduling schemes and the array dispersion structure, the Array-Disperse Based Dual Variable Node Unit (VNU) Cluster Architecture fully leverages the code structure to support at least two physical channels of the Open NAND Flash Interface 5.0 (ONFI 5.0). In addition, the proposed congestion-aware analysis and implementation method achieve a highly parallel decoder at a 70% utilization ratio. Implemented in TSMC 28nm process, the presented decoder provides 38.64 Gbps throughput at RBER=1.456% Bi-AWGN channel with an area of 2.97 mm2.",

author = "Liu, {Li Wei} and MU-HUA YUAN and Liao, {Yen Chin} and Hsie-Chia Chang",

year = "2022",

month = sep,

day = "1",

doi = "10.1109/OJCAS.2022.3203849",

language = "American English",

volume = "3",

pages = "180--191",

journal = "IEEE Open Journal of Circuits and Systems",

}

TY - JOUR

T1 - A 38.64-Gb/s Large-CPM 2-KB LDPC Decoder Implementation for nand Flash Memories

AU - Liu, Li Wei

AU - YUAN, MU-HUA

AU - Liao, Yen Chin

AU - Chang, Hsie-Chia

PY - 2022/9/1

Y1 - 2022/9/1

N2 - The routing congestion over a QC-LDPC decoder with a large circular permutation matrix (CPM) size has long been an obstacle to high throughput designs. This paper presents a large-CPM congestion-free decoder for (18396, 16416) quasi-cyclic Euclidean geometry low-density parity-check (QC-EG-LDPC) code in NAND flash application. Considering area efficiency in scheduling schemes and the array dispersion structure, the Array-Disperse Based Dual Variable Node Unit (VNU) Cluster Architecture fully leverages the code structure to support at least two physical channels of the Open NAND Flash Interface 5.0 (ONFI 5.0). In addition, the proposed congestion-aware analysis and implementation method achieve a highly parallel decoder at a 70% utilization ratio. Implemented in TSMC 28nm process, the presented decoder provides 38.64 Gbps throughput at RBER=1.456% Bi-AWGN channel with an area of 2.97 mm2.

AB - The routing congestion over a QC-LDPC decoder with a large circular permutation matrix (CPM) size has long been an obstacle to high throughput designs. This paper presents a large-CPM congestion-free decoder for (18396, 16416) quasi-cyclic Euclidean geometry low-density parity-check (QC-EG-LDPC) code in NAND flash application. Considering area efficiency in scheduling schemes and the array dispersion structure, the Array-Disperse Based Dual Variable Node Unit (VNU) Cluster Architecture fully leverages the code structure to support at least two physical channels of the Open NAND Flash Interface 5.0 (ONFI 5.0). In addition, the proposed congestion-aware analysis and implementation method achieve a highly parallel decoder at a 70% utilization ratio. Implemented in TSMC 28nm process, the presented decoder provides 38.64 Gbps throughput at RBER=1.456% Bi-AWGN channel with an area of 2.97 mm2.

U2 - 10.1109/OJCAS.2022.3203849

DO - 10.1109/OJCAS.2022.3203849

M3 - Article

VL - 3

SP - 180

EP - 191

JO - IEEE Open Journal of Circuits and Systems

JF - IEEE Open Journal of Circuits and Systems

ER -

A 38.64-Gb/s Large-CPM 2-KB LDPC Decoder Implementation for nand Flash Memories

Abstract

Access to Document

Fingerprint

Cite this