A 3.84 Gbits/s AES crypto coprocessor with modes of operation in a 0.18-μm CMOS technology

Alireza Hodjat; David D. Hwang; Bo-Cheng Lai; Kris Tiri; Ingrid Verbauwhede

doi:10.1145/1057661.1057677

A 3.84 Gbits/s AES crypto coprocessor with modes of operation in a 0.18-μm CMOS technology

Alireza Hodjat^*, David D. Hwang, Bo-Cheng Lai, Kris Tiri, Ingrid Verbauwhede

^*Corresponding author for this work

Institute of Electronics

Research output: Contribution to conference › Paper › peer-review

61 Scopus citations

Abstract

In this paper an AES crypto coprocessor that is fabricated using a 0.18-μm CMOS technology is presented. This crypto coprocessor performs the AES-128 encryption in both feedback and non-feedback modes of operation. A maximum throughput of 3.84 Gbits/s is achieved at a 330 MHz clock frequency for ECB, OFB, and CBC modes of operation. This crypto coprocessor can be programmed using the memory-mapped interface of an embedded CPU core and is tested using a LEON 32-bit (SPARC V8) processor in the ThumbPod secure system-on-chip.

Original language	English
Pages	60-63
Number of pages	4
DOIs	https://doi.org/10.1145/1057661.1057677
State	Published - 29 Dec 2005
Event	2005 ACM Great Lakessymposium on VLSI, GLSVLSI'05 - Chicago, IL, United States Duration: 17 Apr 2005 → 19 Apr 2005

Conference

Conference	2005 ACM Great Lakessymposium on VLSI, GLSVLSI'05
Country/Territory	United States
City	Chicago, IL
Period	17/04/05 → 19/04/05

Keywords

ASIC
Advanced Encryption Standard (AES)
Crypto-processor
Cryptography
FPGA
Hardware architectures
Security
VLSI

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10.1145/1057661.1057677

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AU - Verbauwhede, Ingrid

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A 3.84 Gbits/s AES crypto coprocessor with modes of operation in a 0.18-μm CMOS technology

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Keywords

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