A 3.66Gb/s 275mW TB-LDPC-CC decoder chip for MIMO broadcasting communications

Chih Lung Chen; Yu Cheng Lan; Hsie-Chia Chang; Chen-Yi Lee

doi:10.1109/ASSCC.2013.6691005

A 3.66Gb/s 275mW TB-LDPC-CC decoder chip for MIMO broadcasting communications

Chih Lung Chen^*, Yu Cheng Lan, Hsie-Chia Chang, Chen-Yi Lee

^*Corresponding author for this work

Institute of Electronics

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

8 Scopus citations

Abstract

In this work, a decoder chip for time-invariant tail-biting LDPC convolutional code (TB-LDPC-CC) is proposed. By modifying the layered decoding scheduling, the proposed decoding algorithm can achieve twice faster decoding convergence than the conventional flooding scheduling. Furthermore, 30.77% storage requirement is also reduced due to adaptive channel value addressing employed in memory-based decoder design. The multiple frame sizes handling ability can lower the power and adapt to multiple applications. By integrating these techniques, a TB-LDPC-CC decoder chip supporting three frame sizes is implemented in UMC 90nm CMOS technology. The decoder containing 4 processors occupies 2.18mm² area and provides maximum throughput 3.66Gb/s under 0.8V supply and 305MHz with a 18.8pJ/bit/proc energy efficiency.

Original language	English
Title of host publication	Proceedings of the 2013 IEEE Asian Solid-State Circuits Conference, A-SSCC 2013
Pages	153-156
Number of pages	4
DOIs	https://doi.org/10.1109/ASSCC.2013.6691005
State	Published - 2013
Event	2013 9th IEEE Asian Solid-State Circuits Conference, A-SSCC 2013 - Singapore, Singapore Duration: 11 Nov 2013 → 13 Nov 2013

Publication series

Name	Proceedings of the 2013 IEEE Asian Solid-State Circuits Conference, A-SSCC 2013

Conference

Conference	2013 9th IEEE Asian Solid-State Circuits Conference, A-SSCC 2013
Country/Territory	Singapore
City	Singapore
Period	11/11/13 → 13/11/13

Keywords

High throughput
LDPC-CC
Tail-biting

UN SDGs

This output contributes to the following UN Sustainable Development Goals (SDGs)

Access to Document

10.1109/ASSCC.2013.6691005

Cite this

Chen, C. L., Lan, Y. C., Chang, H.-C., & Lee, C.-Y. (2013). A 3.66Gb/s 275mW TB-LDPC-CC decoder chip for MIMO broadcasting communications. In Proceedings of the 2013 IEEE Asian Solid-State Circuits Conference, A-SSCC 2013 (pp. 153-156). Article 6691005 (Proceedings of the 2013 IEEE Asian Solid-State Circuits Conference, A-SSCC 2013). https://doi.org/10.1109/ASSCC.2013.6691005

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title = "A 3.66Gb/s 275mW TB-LDPC-CC decoder chip for MIMO broadcasting communications",

abstract = "In this work, a decoder chip for time-invariant tail-biting LDPC convolutional code (TB-LDPC-CC) is proposed. By modifying the layered decoding scheduling, the proposed decoding algorithm can achieve twice faster decoding convergence than the conventional flooding scheduling. Furthermore, 30.77% storage requirement is also reduced due to adaptive channel value addressing employed in memory-based decoder design. The multiple frame sizes handling ability can lower the power and adapt to multiple applications. By integrating these techniques, a TB-LDPC-CC decoder chip supporting three frame sizes is implemented in UMC 90nm CMOS technology. The decoder containing 4 processors occupies 2.18mm2 area and provides maximum throughput 3.66Gb/s under 0.8V supply and 305MHz with a 18.8pJ/bit/proc energy efficiency.",

keywords = "High throughput, LDPC-CC, Tail-biting",

author = "Chen, {Chih Lung} and Lan, {Yu Cheng} and Hsie-Chia Chang and Chen-Yi Lee",

year = "2013",

doi = "10.1109/ASSCC.2013.6691005",

language = "English",

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series = "Proceedings of the 2013 IEEE Asian Solid-State Circuits Conference, A-SSCC 2013",

pages = "153--156",

booktitle = "Proceedings of the 2013 IEEE Asian Solid-State Circuits Conference, A-SSCC 2013",

note = "2013 9th IEEE Asian Solid-State Circuits Conference, A-SSCC 2013 ; Conference date: 11-11-2013 Through 13-11-2013",

}

Chen, CL, Lan, YC, Chang, H-C & Lee, C-Y 2013, A 3.66Gb/s 275mW TB-LDPC-CC decoder chip for MIMO broadcasting communications. in Proceedings of the 2013 IEEE Asian Solid-State Circuits Conference, A-SSCC 2013., 6691005, Proceedings of the 2013 IEEE Asian Solid-State Circuits Conference, A-SSCC 2013, pp. 153-156, 2013 9th IEEE Asian Solid-State Circuits Conference, A-SSCC 2013, Singapore, Singapore, 11/11/13. https://doi.org/10.1109/ASSCC.2013.6691005

A 3.66Gb/s 275mW TB-LDPC-CC decoder chip for MIMO broadcasting communications. / Chen, Chih Lung; Lan, Yu Cheng; Chang, Hsie-Chia et al.
Proceedings of the 2013 IEEE Asian Solid-State Circuits Conference, A-SSCC 2013. 2013. p. 153-156 6691005 (Proceedings of the 2013 IEEE Asian Solid-State Circuits Conference, A-SSCC 2013).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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PY - 2013

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N2 - In this work, a decoder chip for time-invariant tail-biting LDPC convolutional code (TB-LDPC-CC) is proposed. By modifying the layered decoding scheduling, the proposed decoding algorithm can achieve twice faster decoding convergence than the conventional flooding scheduling. Furthermore, 30.77% storage requirement is also reduced due to adaptive channel value addressing employed in memory-based decoder design. The multiple frame sizes handling ability can lower the power and adapt to multiple applications. By integrating these techniques, a TB-LDPC-CC decoder chip supporting three frame sizes is implemented in UMC 90nm CMOS technology. The decoder containing 4 processors occupies 2.18mm2 area and provides maximum throughput 3.66Gb/s under 0.8V supply and 305MHz with a 18.8pJ/bit/proc energy efficiency.

AB - In this work, a decoder chip for time-invariant tail-biting LDPC convolutional code (TB-LDPC-CC) is proposed. By modifying the layered decoding scheduling, the proposed decoding algorithm can achieve twice faster decoding convergence than the conventional flooding scheduling. Furthermore, 30.77% storage requirement is also reduced due to adaptive channel value addressing employed in memory-based decoder design. The multiple frame sizes handling ability can lower the power and adapt to multiple applications. By integrating these techniques, a TB-LDPC-CC decoder chip supporting three frame sizes is implemented in UMC 90nm CMOS technology. The decoder containing 4 processors occupies 2.18mm2 area and provides maximum throughput 3.66Gb/s under 0.8V supply and 305MHz with a 18.8pJ/bit/proc energy efficiency.

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A 3.66Gb/s 275mW TB-LDPC-CC decoder chip for MIMO broadcasting communications

Abstract

Publication series

Conference

Keywords

UN SDGs

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