A 3.52 Gb/s mmWave baseband with delayed decision feedback sequence estimation in 40 nm

Nicholas Preyss; Christian Senning; Andreas Burg; Wei Chang Liu; Chun Yi Liu; Shyh-Jye Jou

doi:10.1109/ASSCC.2015.7387455

A 3.52 Gb/s mmWave baseband with delayed decision feedback sequence estimation in 40 nm

Nicholas Preyss, Christian Senning, Andreas Burg, Wei Chang Liu, Chun Yi Liu, Shyh-Jye Jou

Institute of Electronics

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

Abstract

We present a digital baseband ASIC for 60 GHz single-carrier (SC) transmission that is optimized for communication scenarios in which most of the energy is concentrated in the first few channel taps. Such scenarios occur for example in office environments with strong reflections. Our circuit targets close-to-optimum maximum-likelihood performance under such conditions. To this end, we show for the first time how a reduced-state-sequence-estimation algorithm can be realized for the 1760 MHz bandwidth of the IEEE 802.11ad standard. The equalizer is complemented in the frontend by a synchronization unit for frequency offset compensation as well as a Golay-sequence based channel estimator and in the backend by an low density parity check (LDPC) decoder. In 40nm CMOS we achieve a measured data rate of up to 3.52 Gb/s using QPSK modulation.

Original language	English
Title of host publication	2015 IEEE Asian Solid-State Circuits Conference, A-SSCC 2015 - Proceedings
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)	9781467371919
DOIs	https://doi.org/10.1109/ASSCC.2015.7387455
State	Published - 19 Jan 2016
Event	11th IEEE Asian Solid-State Circuits Conference, A-SSCC 2015 - Xiamen, Fujian, China Duration: 9 Nov 2015 → 11 Nov 2015

Publication series

Name	2015 IEEE Asian Solid-State Circuits Conference, A-SSCC 2015 - Proceedings

Conference

Conference	11th IEEE Asian Solid-State Circuits Conference, A-SSCC 2015
Country/Territory	China
City	Xiamen, Fujian
Period	9/11/15 → 11/11/15

Access to Document

10.1109/ASSCC.2015.7387455

Cite this

Preyss, N., Senning, C., Burg, A., Liu, W. C., Liu, C. Y., & Jou, S-J. (2016). A 3.52 Gb/s mmWave baseband with delayed decision feedback sequence estimation in 40 nm. In 2015 IEEE Asian Solid-State Circuits Conference, A-SSCC 2015 - Proceedings [7387455] (2015 IEEE Asian Solid-State Circuits Conference, A-SSCC 2015 - Proceedings). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ASSCC.2015.7387455

@inproceedings{fa74621888d1448bab7530d49e97b72b,

title = "A 3.52 Gb/s mmWave baseband with delayed decision feedback sequence estimation in 40 nm",

abstract = "We present a digital baseband ASIC for 60 GHz single-carrier (SC) transmission that is optimized for communication scenarios in which most of the energy is concentrated in the first few channel taps. Such scenarios occur for example in office environments with strong reflections. Our circuit targets close-to-optimum maximum-likelihood performance under such conditions. To this end, we show for the first time how a reduced-state-sequence-estimation algorithm can be realized for the 1760 MHz bandwidth of the IEEE 802.11ad standard. The equalizer is complemented in the frontend by a synchronization unit for frequency offset compensation as well as a Golay-sequence based channel estimator and in the backend by an low density parity check (LDPC) decoder. In 40nm CMOS we achieve a measured data rate of up to 3.52 Gb/s using QPSK modulation.",

author = "Nicholas Preyss and Christian Senning and Andreas Burg and Liu, {Wei Chang} and Liu, {Chun Yi} and Shyh-Jye Jou",

year = "2016",

month = jan,

day = "19",

doi = "10.1109/ASSCC.2015.7387455",

language = "English",

series = "2015 IEEE Asian Solid-State Circuits Conference, A-SSCC 2015 - Proceedings",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

booktitle = "2015 IEEE Asian Solid-State Circuits Conference, A-SSCC 2015 - Proceedings",

address = "United States",

note = "null ; Conference date: 09-11-2015 Through 11-11-2015",

}

Preyss, N, Senning, C, Burg, A, Liu, WC, Liu, CY & Jou, S-J 2016, A 3.52 Gb/s mmWave baseband with delayed decision feedback sequence estimation in 40 nm. in 2015 IEEE Asian Solid-State Circuits Conference, A-SSCC 2015 - Proceedings., 7387455, 2015 IEEE Asian Solid-State Circuits Conference, A-SSCC 2015 - Proceedings, Institute of Electrical and Electronics Engineers Inc., 11th IEEE Asian Solid-State Circuits Conference, A-SSCC 2015, Xiamen, Fujian, China, 9/11/15. https://doi.org/10.1109/ASSCC.2015.7387455

A 3.52 Gb/s mmWave baseband with delayed decision feedback sequence estimation in 40 nm. / Preyss, Nicholas; Senning, Christian; Burg, Andreas et al.

2015 IEEE Asian Solid-State Circuits Conference, A-SSCC 2015 - Proceedings. Institute of Electrical and Electronics Engineers Inc., 2016. 7387455 (2015 IEEE Asian Solid-State Circuits Conference, A-SSCC 2015 - Proceedings).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - A 3.52 Gb/s mmWave baseband with delayed decision feedback sequence estimation in 40 nm

AU - Preyss, Nicholas

AU - Senning, Christian

AU - Burg, Andreas

AU - Liu, Wei Chang

AU - Liu, Chun Yi

AU - Jou, Shyh-Jye

PY - 2016/1/19

Y1 - 2016/1/19

N2 - We present a digital baseband ASIC for 60 GHz single-carrier (SC) transmission that is optimized for communication scenarios in which most of the energy is concentrated in the first few channel taps. Such scenarios occur for example in office environments with strong reflections. Our circuit targets close-to-optimum maximum-likelihood performance under such conditions. To this end, we show for the first time how a reduced-state-sequence-estimation algorithm can be realized for the 1760 MHz bandwidth of the IEEE 802.11ad standard. The equalizer is complemented in the frontend by a synchronization unit for frequency offset compensation as well as a Golay-sequence based channel estimator and in the backend by an low density parity check (LDPC) decoder. In 40nm CMOS we achieve a measured data rate of up to 3.52 Gb/s using QPSK modulation.

AB - We present a digital baseband ASIC for 60 GHz single-carrier (SC) transmission that is optimized for communication scenarios in which most of the energy is concentrated in the first few channel taps. Such scenarios occur for example in office environments with strong reflections. Our circuit targets close-to-optimum maximum-likelihood performance under such conditions. To this end, we show for the first time how a reduced-state-sequence-estimation algorithm can be realized for the 1760 MHz bandwidth of the IEEE 802.11ad standard. The equalizer is complemented in the frontend by a synchronization unit for frequency offset compensation as well as a Golay-sequence based channel estimator and in the backend by an low density parity check (LDPC) decoder. In 40nm CMOS we achieve a measured data rate of up to 3.52 Gb/s using QPSK modulation.

UR - http://www.scopus.com/inward/record.url?scp=84963847204&partnerID=8YFLogxK

U2 - 10.1109/ASSCC.2015.7387455

DO - 10.1109/ASSCC.2015.7387455

M3 - Conference contribution

AN - SCOPUS:84963847204

T3 - 2015 IEEE Asian Solid-State Circuits Conference, A-SSCC 2015 - Proceedings

BT - 2015 IEEE Asian Solid-State Circuits Conference, A-SSCC 2015 - Proceedings

PB - Institute of Electrical and Electronics Engineers Inc.

Y2 - 9 November 2015 through 11 November 2015

ER -

Preyss N, Senning C, Burg A, Liu WC, Liu CY, Jou S-J. A 3.52 Gb/s mmWave baseband with delayed decision feedback sequence estimation in 40 nm. In 2015 IEEE Asian Solid-State Circuits Conference, A-SSCC 2015 - Proceedings. Institute of Electrical and Electronics Engineers Inc. 2016. 7387455. (2015 IEEE Asian Solid-State Circuits Conference, A-SSCC 2015 - Proceedings). doi: 10.1109/ASSCC.2015.7387455

A 3.52 Gb/s mmWave baseband with delayed decision feedback sequence estimation in 40 nm

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