A 35μW 96.8dB SNDR 1 kHz BW multi-step incremental ADC using multi-slope extended counting with a single integrator

Yi Zhang, Chia-Hung Chen, Tao He, Gabor C. Temes

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

9 Scopus citations

Abstract

A multi-step incremental ADC (IADC) with multi-slope extended counting is presented. In the proposed IADC, the accuracy is enhanced by reconfiguring it as a multi-slope ADC in two additional steps. For the same accuracy, the conversion cycle is shortened by a factor of about 29 as compared to the single-step IADC. Fabricated in 0.18-μm CMOS process, the prototype ADC operates at 642 kHz and achieves a peak SNDR = 96.8 dB and DR = 99.7 dB over a 1 kHz bandwidth. The power consumption is 35 μW, which results in an excellent Schreier FoM of 174.6 dB.

Original languageEnglish
Title of host publication2016 IEEE Symposium on VLSI Circuits, VLSI Circuits 2016
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9781509006342
DOIs
StatePublished - 21 Sep 2016
Event30th IEEE Symposium on VLSI Circuits, VLSI Circuits 2016 - Honolulu, United States
Duration: 14 Jun 201617 Jun 2016

Publication series

NameIEEE Symposium on VLSI Circuits, Digest of Technical Papers
Volume2016-September

Conference

Conference30th IEEE Symposium on VLSI Circuits, VLSI Circuits 2016
Country/TerritoryUnited States
CityHonolulu
Period14/06/1617/06/16

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