@inproceedings{2d0529fc73f14de5b9adc0b1d5ab2395,
title = "A 35μW 96.8dB SNDR 1 kHz BW multi-step incremental ADC using multi-slope extended counting with a single integrator",
abstract = "A multi-step incremental ADC (IADC) with multi-slope extended counting is presented. In the proposed IADC, the accuracy is enhanced by reconfiguring it as a multi-slope ADC in two additional steps. For the same accuracy, the conversion cycle is shortened by a factor of about 29 as compared to the single-step IADC. Fabricated in 0.18-μm CMOS process, the prototype ADC operates at 642 kHz and achieves a peak SNDR = 96.8 dB and DR = 99.7 dB over a 1 kHz bandwidth. The power consumption is 35 μW, which results in an excellent Schreier FoM of 174.6 dB.",
author = "Yi Zhang and Chia-Hung Chen and Tao He and Temes, {Gabor C.}",
year = "2016",
month = sep,
day = "21",
doi = "10.1109/VLSIC.2016.7573464",
language = "English",
series = "IEEE Symposium on VLSI Circuits, Digest of Technical Papers",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
booktitle = "2016 IEEE Symposium on VLSI Circuits, VLSI Circuits 2016",
address = "United States",
note = "30th IEEE Symposium on VLSI Circuits, VLSI Circuits 2016 ; Conference date: 14-06-2016 Through 17-06-2016",
}