TY - GEN
T1 - A 32 Gb/s PAM-4 optical transceiver with active back termination in 40 nm CMOS technology
AU - Ho, Wei Hsiang
AU - Hsieh, Yi Hsun
AU - Murmann, Boris
AU - Chen, Wei Zen
N1 - Publisher Copyright:
© 2020 IEEE
PY - 2020/10
Y1 - 2020/10
N2 - This paper describes the design of a 32 Gb/s four-level pulse amplitude modulation (PAM-4) optical transceiver in a 40 nm CMOS technology. At the transmitter side, the laser driver is composed of an asymmetric waveform equalizer, a 3-tap feed-forward equalizer (FFE), and a novel active-back termination (ABT) circuit. The ABT circuit provides a self-tracking, tunable source impedance to match the characteristic impedance of different laser diodes. At the receiver side, the fully integrated optical receiver consists of a transimpedance amplifier, a variable gain amplifier, an automatic threshold tracking circuit (ATC), and a quarter-rate decision feedback equalizer (DFE). By using the adaptive ATC, it reduces the BER induced by the harmonic distortion along the signal path by more than 27X. Both the ATC and DFE are automatically adapted by an on-chip sign-sign LMS (SSLMS) engine. Fabricated in TSMC 40 nm CMOS process, the chip area for the transmitter and receiver are about 0.029 mm2 and 0.23 mm2. The power consumptions are about 146.8 mW and 128.8 mW respectively for the PAM-4 transmitter and receiver.
AB - This paper describes the design of a 32 Gb/s four-level pulse amplitude modulation (PAM-4) optical transceiver in a 40 nm CMOS technology. At the transmitter side, the laser driver is composed of an asymmetric waveform equalizer, a 3-tap feed-forward equalizer (FFE), and a novel active-back termination (ABT) circuit. The ABT circuit provides a self-tracking, tunable source impedance to match the characteristic impedance of different laser diodes. At the receiver side, the fully integrated optical receiver consists of a transimpedance amplifier, a variable gain amplifier, an automatic threshold tracking circuit (ATC), and a quarter-rate decision feedback equalizer (DFE). By using the adaptive ATC, it reduces the BER induced by the harmonic distortion along the signal path by more than 27X. Both the ATC and DFE are automatically adapted by an on-chip sign-sign LMS (SSLMS) engine. Fabricated in TSMC 40 nm CMOS process, the chip area for the transmitter and receiver are about 0.029 mm2 and 0.23 mm2. The power consumptions are about 146.8 mW and 128.8 mW respectively for the PAM-4 transmitter and receiver.
KW - Active back termination
KW - Automatic threshold tracking
KW - DFE
KW - FFE
KW - PAM4 transceiver
UR - http://www.scopus.com/inward/record.url?scp=85098127788&partnerID=8YFLogxK
U2 - 10.1109/ISCAS45731.2020.9180483
DO - 10.1109/ISCAS45731.2020.9180483
M3 - Conference contribution
AN - SCOPUS:85098127788
T3 - Proceedings - IEEE International Symposium on Circuits and Systems
BT - 2020 IEEE International Symposium on Circuits and Systems, ISCAS 2020 - Proceedings
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 52nd IEEE International Symposium on Circuits and Systems, ISCAS 2020
Y2 - 10 October 2020 through 21 October 2020
ER -