A 3.12 pJ/bit, 19-27 Gbps receiver with 2 Tap-DFE embedded clock and data recovery

Zheng Hao Hong; Wei-Zen Chen

doi:10.1109/ASSCC.2014.7008914

A 3.12 pJ/bit, 19-27 Gbps receiver with 2 Tap-DFE embedded clock and data recovery

Zheng Hao Hong, Wei-Zen Chen

Institute of Electronics

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

1 Scopus citations

Abstract

A 19-27-Gb/s receiver comprising of a continuous time linear equalizer (CTLE) followed by a 2 tap decision feedback equalizer embedded clock and data recovery circuit is implemented. The hybrid CDR is operated at half rate, which is incorporated into a broad band PLL to facilitate ISI and jitter suppression over wide band operation. A quadrature relaxation type oscillator is proposed to provide the sampling phases without bulky inductors. Fabricated in a 40 nm CMOS technology, the whole receiver manifests a high energy efficiency of 3.12pJ/bit at 27 Gbps operation to compensate 20 dB channel loss at Nyquist frequency. The core area is 0.09 mm² only.

Original language	English
Title of host publication	2014 IEEE Asian Solid-State Circuits Conference, A-SSCC - Proceedings of Technical Papers
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	277-280
Number of pages	4
ISBN (Electronic)	9781479940905
DOIs	https://doi.org/10.1109/ASSCC.2014.7008914
State	Published - 10 Nov 2014
Event	2014 10th IEEE Asian Solid-State Circuits Conference, A-SSCC 2014 - Kaohsiung, Taiwan Duration: 10 Nov 2014 → 12 Nov 2014

Publication series

Name	2014 IEEE Asian Solid-State Circuits Conference, A-SSCC - Proceedings of Technical Papers

Conference

Conference	2014 10th IEEE Asian Solid-State Circuits Conference, A-SSCC 2014
Country/Territory	Taiwan
City	Kaohsiung
Period	10/11/14 → 12/11/14

Keywords

CDR
CTLE
DFE
PLL

UN SDGs

This output contributes to the following UN Sustainable Development Goals (SDGs)

Access to Document

10.1109/ASSCC.2014.7008914

Cite this

Hong, Z. H., & Chen, W.-Z. (2014). A 3.12 pJ/bit, 19-27 Gbps receiver with 2 Tap-DFE embedded clock and data recovery. In 2014 IEEE Asian Solid-State Circuits Conference, A-SSCC - Proceedings of Technical Papers (pp. 277-280). Article 7008914 (2014 IEEE Asian Solid-State Circuits Conference, A-SSCC - Proceedings of Technical Papers). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ASSCC.2014.7008914

Hong, Zheng Hao ; Chen, Wei-Zen. / A 3.12 pJ/bit, 19-27 Gbps receiver with 2 Tap-DFE embedded clock and data recovery. 2014 IEEE Asian Solid-State Circuits Conference, A-SSCC - Proceedings of Technical Papers. Institute of Electrical and Electronics Engineers Inc., 2014. pp. 277-280 (2014 IEEE Asian Solid-State Circuits Conference, A-SSCC - Proceedings of Technical Papers).

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abstract = "A 19-27-Gb/s receiver comprising of a continuous time linear equalizer (CTLE) followed by a 2 tap decision feedback equalizer embedded clock and data recovery circuit is implemented. The hybrid CDR is operated at half rate, which is incorporated into a broad band PLL to facilitate ISI and jitter suppression over wide band operation. A quadrature relaxation type oscillator is proposed to provide the sampling phases without bulky inductors. Fabricated in a 40 nm CMOS technology, the whole receiver manifests a high energy efficiency of 3.12pJ/bit at 27 Gbps operation to compensate 20 dB channel loss at Nyquist frequency. The core area is 0.09 mm2 only.",

keywords = "CDR, CTLE, DFE, PLL",

author = "Hong, {Zheng Hao} and Wei-Zen Chen",

note = "Publisher Copyright: {\textcopyright} 2014 IEEE.; 2014 10th IEEE Asian Solid-State Circuits Conference, A-SSCC 2014 ; Conference date: 10-11-2014 Through 12-11-2014",

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series = "2014 IEEE Asian Solid-State Circuits Conference, A-SSCC - Proceedings of Technical Papers",

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Hong, ZH & Chen, W-Z 2014, A 3.12 pJ/bit, 19-27 Gbps receiver with 2 Tap-DFE embedded clock and data recovery. in 2014 IEEE Asian Solid-State Circuits Conference, A-SSCC - Proceedings of Technical Papers., 7008914, 2014 IEEE Asian Solid-State Circuits Conference, A-SSCC - Proceedings of Technical Papers, Institute of Electrical and Electronics Engineers Inc., pp. 277-280, 2014 10th IEEE Asian Solid-State Circuits Conference, A-SSCC 2014, Kaohsiung, Taiwan, 10/11/14. https://doi.org/10.1109/ASSCC.2014.7008914

A 3.12 pJ/bit, 19-27 Gbps receiver with 2 Tap-DFE embedded clock and data recovery. / Hong, Zheng Hao; Chen, Wei-Zen.
2014 IEEE Asian Solid-State Circuits Conference, A-SSCC - Proceedings of Technical Papers. Institute of Electrical and Electronics Engineers Inc., 2014. p. 277-280 7008914 (2014 IEEE Asian Solid-State Circuits Conference, A-SSCC - Proceedings of Technical Papers).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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AU - Chen, Wei-Zen

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N2 - A 19-27-Gb/s receiver comprising of a continuous time linear equalizer (CTLE) followed by a 2 tap decision feedback equalizer embedded clock and data recovery circuit is implemented. The hybrid CDR is operated at half rate, which is incorporated into a broad band PLL to facilitate ISI and jitter suppression over wide band operation. A quadrature relaxation type oscillator is proposed to provide the sampling phases without bulky inductors. Fabricated in a 40 nm CMOS technology, the whole receiver manifests a high energy efficiency of 3.12pJ/bit at 27 Gbps operation to compensate 20 dB channel loss at Nyquist frequency. The core area is 0.09 mm2 only.

AB - A 19-27-Gb/s receiver comprising of a continuous time linear equalizer (CTLE) followed by a 2 tap decision feedback equalizer embedded clock and data recovery circuit is implemented. The hybrid CDR is operated at half rate, which is incorporated into a broad band PLL to facilitate ISI and jitter suppression over wide band operation. A quadrature relaxation type oscillator is proposed to provide the sampling phases without bulky inductors. Fabricated in a 40 nm CMOS technology, the whole receiver manifests a high energy efficiency of 3.12pJ/bit at 27 Gbps operation to compensate 20 dB channel loss at Nyquist frequency. The core area is 0.09 mm2 only.

KW - CDR

KW - CTLE

KW - DFE

KW - PLL

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M3 - Conference contribution

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BT - 2014 IEEE Asian Solid-State Circuits Conference, A-SSCC - Proceedings of Technical Papers

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ER -

Hong ZH, Chen WZ. A 3.12 pJ/bit, 19-27 Gbps receiver with 2 Tap-DFE embedded clock and data recovery. In 2014 IEEE Asian Solid-State Circuits Conference, A-SSCC - Proceedings of Technical Papers. Institute of Electrical and Electronics Engineers Inc. 2014. p. 277-280. 7008914. (2014 IEEE Asian Solid-State Circuits Conference, A-SSCC - Proceedings of Technical Papers). doi: 10.1109/ASSCC.2014.7008914

A 3.12 pJ/bit, 19-27 Gbps receiver with 2 Tap-DFE embedded clock and data recovery

Abstract

Publication series

Conference

Keywords

UN SDGs

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