A 2kb built-in row-controlled dynamic voltage scaling near-/sub-threshold FIFO memory for WBANs

Wei Hung Du; Po-Tsang Huang; Ming Hung Chang; Wei Hwang

doi:10.1109/VLSI-DAT.2012.6212588

A 2kb built-in row-controlled dynamic voltage scaling near-/sub-threshold FIFO memory for WBANs

Wei Hung Du^*, Po-Tsang Huang, Ming Hung Chang, Wei Hwang

^*Corresponding author for this work

International College of Semiconductor Technology

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

1 Scopus citations

Abstract

Due to the limited energy source, ultra-low power designs are significant approaches in energy-constrained SoCs. In this paper, a 2kb built-in row-controlled dynamic voltage scaling (DVS) FIFO memory is proposed to adopt the operation voltage in the near-/sub-threshold regions for the WBAN (wireless body area network) system. The row-based DVS provides the fine-grained power switch control for each sub-block. Therefore, the switching energy can be reduced, and the switching setup time can be eliminated. Moreover, only one sub-block are operated in the typical mode, and other sub-blocks are operated in the low-power mode and cut-off mode for realizing the power saving. Based on TSMC 65nm technology, the proposed DVS FIFO can achieve 47.8% power saving.

Original language	English
Title of host publication	2012 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2012 - Proceedings of Technical Papers
DOIs	https://doi.org/10.1109/VLSI-DAT.2012.6212588
State	Published - 2012
Event	2012 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2012 - Hsinchu, Taiwan Duration: 23 Apr 2012 → 25 Apr 2012

Publication series

Name	2012 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2012 - Proceedings of Technical Papers

Conference

Conference	2012 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2012
Country/Territory	Taiwan
City	Hsinchu
Period	23/04/12 → 25/04/12

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10.1109/VLSI-DAT.2012.6212588

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Du, W. H., Huang, P.-T., Chang, M. H., & Hwang, W. (2012). A 2kb built-in row-controlled dynamic voltage scaling near-/sub-threshold FIFO memory for WBANs. In 2012 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2012 - Proceedings of Technical Papers Article 6212588 (2012 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2012 - Proceedings of Technical Papers). https://doi.org/10.1109/VLSI-DAT.2012.6212588

Du, Wei Hung ; Huang, Po-Tsang ; Chang, Ming Hung et al. / A 2kb built-in row-controlled dynamic voltage scaling near-/sub-threshold FIFO memory for WBANs. 2012 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2012 - Proceedings of Technical Papers. 2012. (2012 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2012 - Proceedings of Technical Papers).

@inproceedings{bdb40ec4757f4dac908e3d91e3ad2e52,

title = "A 2kb built-in row-controlled dynamic voltage scaling near-/sub-threshold FIFO memory for WBANs",

abstract = "Due to the limited energy source, ultra-low power designs are significant approaches in energy-constrained SoCs. In this paper, a 2kb built-in row-controlled dynamic voltage scaling (DVS) FIFO memory is proposed to adopt the operation voltage in the near-/sub-threshold regions for the WBAN (wireless body area network) system. The row-based DVS provides the fine-grained power switch control for each sub-block. Therefore, the switching energy can be reduced, and the switching setup time can be eliminated. Moreover, only one sub-block are operated in the typical mode, and other sub-blocks are operated in the low-power mode and cut-off mode for realizing the power saving. Based on TSMC 65nm technology, the proposed DVS FIFO can achieve 47.8% power saving.",

author = "Du, {Wei Hung} and Po-Tsang Huang and Chang, {Ming Hung} and Wei Hwang",

year = "2012",

doi = "10.1109/VLSI-DAT.2012.6212588",

language = "English",

isbn = "9781457720819",

series = "2012 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2012 - Proceedings of Technical Papers",

booktitle = "2012 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2012 - Proceedings of Technical Papers",

note = "2012 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2012 ; Conference date: 23-04-2012 Through 25-04-2012",

}

Du, WH, Huang, P-T, Chang, MH & Hwang, W 2012, A 2kb built-in row-controlled dynamic voltage scaling near-/sub-threshold FIFO memory for WBANs. in 2012 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2012 - Proceedings of Technical Papers., 6212588, 2012 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2012 - Proceedings of Technical Papers, 2012 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2012, Hsinchu, Taiwan, 23/04/12. https://doi.org/10.1109/VLSI-DAT.2012.6212588

A 2kb built-in row-controlled dynamic voltage scaling near-/sub-threshold FIFO memory for WBANs. / Du, Wei Hung; Huang, Po-Tsang; Chang, Ming Hung et al.
2012 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2012 - Proceedings of Technical Papers. 2012. 6212588 (2012 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2012 - Proceedings of Technical Papers).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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T1 - A 2kb built-in row-controlled dynamic voltage scaling near-/sub-threshold FIFO memory for WBANs

AU - Du, Wei Hung

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AU - Chang, Ming Hung

AU - Hwang, Wei

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N2 - Due to the limited energy source, ultra-low power designs are significant approaches in energy-constrained SoCs. In this paper, a 2kb built-in row-controlled dynamic voltage scaling (DVS) FIFO memory is proposed to adopt the operation voltage in the near-/sub-threshold regions for the WBAN (wireless body area network) system. The row-based DVS provides the fine-grained power switch control for each sub-block. Therefore, the switching energy can be reduced, and the switching setup time can be eliminated. Moreover, only one sub-block are operated in the typical mode, and other sub-blocks are operated in the low-power mode and cut-off mode for realizing the power saving. Based on TSMC 65nm technology, the proposed DVS FIFO can achieve 47.8% power saving.

AB - Due to the limited energy source, ultra-low power designs are significant approaches in energy-constrained SoCs. In this paper, a 2kb built-in row-controlled dynamic voltage scaling (DVS) FIFO memory is proposed to adopt the operation voltage in the near-/sub-threshold regions for the WBAN (wireless body area network) system. The row-based DVS provides the fine-grained power switch control for each sub-block. Therefore, the switching energy can be reduced, and the switching setup time can be eliminated. Moreover, only one sub-block are operated in the typical mode, and other sub-blocks are operated in the low-power mode and cut-off mode for realizing the power saving. Based on TSMC 65nm technology, the proposed DVS FIFO can achieve 47.8% power saving.

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Du WH, Huang PT, Chang MH, Hwang W. A 2kb built-in row-controlled dynamic voltage scaling near-/sub-threshold FIFO memory for WBANs. In 2012 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2012 - Proceedings of Technical Papers. 2012. 6212588. (2012 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2012 - Proceedings of Technical Papers). doi: 10.1109/VLSI-DAT.2012.6212588

A 2kb built-in row-controlled dynamic voltage scaling near-/sub-threshold FIFO memory for WBANs

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