A 2.97 Gb/s DPA-resistant AES engine with self-generated random sequence

Po Chun Liu; Ju Hung Hsiao; Hsie-Chia Chang; Chen-Yi Lee

doi:10.1109/ESSCIRC.2011.6044917

A 2.97 Gb/s DPA-resistant AES engine with self-generated random sequence

Po Chun Liu^*, Ju Hung Hsiao, Hsie-Chia Chang, Chen-Yi Lee

^*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

14 Scopus citations

Abstract

This paper presents a DPA-resistant AES crypto engine. The DPA countermeasure circuit is combined with a self-generated random number generator to eliminate an extra circuit for generating random bits. The cell area for the DPA-resistant AES crypto engine is 0.104 mm² in UMC 90 nm CMOS technology, which is only 6.2% larger than an unprotected AES engine. The maximum operating frequency of the AES engine is 255 MHz, resulting in 2.97 Gb/s throughput. Since the DPA countermeasure circuit works in parallel with the AES engine, no throughput degradation is incurred with the proposed architecture. The proposed DPA-resistant AES engine has significant improvements over previous state-of-the-art designs.

Original language	English
Title of host publication	ESSCIRC 2011 - Proceedings of the 37th European Solid-State Circuits Conference
Pages	71-74
Number of pages	4
DOIs	https://doi.org/10.1109/ESSCIRC.2011.6044917
State	Published - 12 Dec 2011
Event	37th European Solid-State Circuits Conference, ESSCIRC 2011 - Helsinki, Finland Duration: 12 Sep 2011 → 16 Sep 2011

Publication series

Name	European Solid-State Circuits Conference
ISSN (Print)	1930-8833

Conference

Conference	37th European Solid-State Circuits Conference, ESSCIRC 2011
Country/Territory	Finland
City	Helsinki
Period	12/09/11 → 16/09/11

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10.1109/ESSCIRC.2011.6044917

Cite this

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title = "A 2.97 Gb/s DPA-resistant AES engine with self-generated random sequence",

abstract = "This paper presents a DPA-resistant AES crypto engine. The DPA countermeasure circuit is combined with a self-generated random number generator to eliminate an extra circuit for generating random bits. The cell area for the DPA-resistant AES crypto engine is 0.104 mm2 in UMC 90 nm CMOS technology, which is only 6.2% larger than an unprotected AES engine. The maximum operating frequency of the AES engine is 255 MHz, resulting in 2.97 Gb/s throughput. Since the DPA countermeasure circuit works in parallel with the AES engine, no throughput degradation is incurred with the proposed architecture. The proposed DPA-resistant AES engine has significant improvements over previous state-of-the-art designs.",

author = "Liu, {Po Chun} and Hsiao, {Ju Hung} and Hsie-Chia Chang and Chen-Yi Lee",

year = "2011",

month = dec,

day = "12",

doi = "10.1109/ESSCIRC.2011.6044917",

language = "English",

isbn = "9781457707018",

series = "European Solid-State Circuits Conference",

pages = "71--74",

booktitle = "ESSCIRC 2011 - Proceedings of the 37th European Solid-State Circuits Conference",

note = "37th European Solid-State Circuits Conference, ESSCIRC 2011 ; Conference date: 12-09-2011 Through 16-09-2011",

}

Liu, PC, Hsiao, JH, Chang, H-C & Lee, C-Y 2011, A 2.97 Gb/s DPA-resistant AES engine with self-generated random sequence. in ESSCIRC 2011 - Proceedings of the 37th European Solid-State Circuits Conference., 6044917, European Solid-State Circuits Conference, pp. 71-74, 37th European Solid-State Circuits Conference, ESSCIRC 2011, Helsinki, Finland, 12/09/11. https://doi.org/10.1109/ESSCIRC.2011.6044917

A 2.97 Gb/s DPA-resistant AES engine with self-generated random sequence. / Liu, Po Chun; Hsiao, Ju Hung; Chang, Hsie-Chia et al.
ESSCIRC 2011 - Proceedings of the 37th European Solid-State Circuits Conference. 2011. p. 71-74 6044917 (European Solid-State Circuits Conference).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

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AB - This paper presents a DPA-resistant AES crypto engine. The DPA countermeasure circuit is combined with a self-generated random number generator to eliminate an extra circuit for generating random bits. The cell area for the DPA-resistant AES crypto engine is 0.104 mm2 in UMC 90 nm CMOS technology, which is only 6.2% larger than an unprotected AES engine. The maximum operating frequency of the AES engine is 255 MHz, resulting in 2.97 Gb/s throughput. Since the DPA countermeasure circuit works in parallel with the AES engine, no throughput degradation is incurred with the proposed architecture. The proposed DPA-resistant AES engine has significant improvements over previous state-of-the-art designs.

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A 2.97 Gb/s DPA-resistant AES engine with self-generated random sequence

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