A 28mW OFDM baseband receiver chip for DVB-T/H with all digital synchronization

Ting Chen Wei*, Wei Chang Liu, Chi Yao Tseng, Syu Siang Long, Shyh-Jye Jou, Muh Tian Shiue

*Corresponding author for this work

    Research output: Contribution to journalConference articlepeer-review

    3 Scopus citations


    An OFDM baseband receiver chip for DVB-T/H application is proposed In this paper. With all-digital jointed detection/synchronization loops and channel estimation, the proposed receiver chip can compensate 200ppm sampling clock offset (SCO) and ± 50 subcarrier spacing carrier frequency offset (CFO) In multipath environment. The total memory requirement of this chip is 102.8KB and the total equivalent gate count (Including memory) is about 806,800 gates. By using 0.18μm CMOS process, the power consumption is 28mW at 1.45 V, 40MHz and core size of this chip is 3600μm × 3600μm.

    Original languageEnglish
    Article number4672094
    Pages (from-to)351-354
    Number of pages4
    JournalProceedings of the Custom Integrated Circuits Conference
    StatePublished - 26 Dec 2008
    EventIEEE 2008 Custom Integrated Circuits Conference, CICC 2008 - San Jose, CA, United States
    Duration: 21 Sep 200824 Sep 2008


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