A 26.9K 314.5Mbps soft (32400, 32208) BCH decoder chip for DVB-S2 system

Yi Min Lin*, Chih Lung Chen*, Hsie-Chia Chang, Chen-Yi Lee

*Corresponding author for this work

    Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

    1 Scopus citations

    Abstract

    This paper provides a soft BCH decoder using error magnitudes to deal with least reliable bits. With soft information from the previous decoder defined in digital video broadcasting (DVB), the proposed soft BCH decoder provides much lower complexity and latency than the traditional hard BCH decoder while still maintaining performance. The proposed error locator evaluator architecture evaluates error locations without Chien search, leading to high throughput. Börck-Pereyra error magnitudes solvers (BP-EMS) is presented to improve decoding efficiency and hardware complexity. The experimental result reveals that our proposed soft (32400, 32208) BCH decoder defined in DVB-S2 system can save 50.0% gate-count and achieve 314.5Mbps in standard CMOS 90nm technology.

    Original languageEnglish
    Title of host publicationProceedings of Technical Papers - 2009 IEEE Asian Solid-State Circuits Conference, A-SSCC 2009
    Pages373-376
    Number of pages4
    DOIs
    StatePublished - 1 Dec 2009
    Event2009 IEEE Asian Solid-State Circuits Conference, A-SSCC 2009 - Taipei, Taiwan
    Duration: 16 Nov 200918 Nov 2009

    Publication series

    NameProceedings of Technical Papers - 2009 IEEE Asian Solid-State Circuits Conference, A-SSCC 2009

    Conference

    Conference2009 IEEE Asian Solid-State Circuits Conference, A-SSCC 2009
    Country/TerritoryTaiwan
    CityTaipei
    Period16/11/0918/11/09

    Keywords

    • Bose-Chaudhuri-Hochquenghem (BCH) codes
    • Digital video broadcasting
    • Error correction coding

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