A 26.9 K 314.5 Mb/s soft (32400,32208) BCH decoder chip for DVB-S2 system

Yi Min Lin*, Chih Lung Chen, Hsie-Chia Chang, Chen-Yi Lee

*Corresponding author for this work

    Research output: Contribution to journalArticlepeer-review

    15 Scopus citations

    Abstract

    This paper provides a soft BoseChaudhuriHochquenghem (BCH) decoder chip with soft information from the LDPC decoder for the DVB-S2 system. In contrast with the hard BCH decoder, the proposed soft BCH decoder that deals with least reliable bits can provide much lower complexity with similar error-correcting performance. Moreover, the error locator evaluator is proposed to evaluate error locations without the Chien search for higher throughput, and the Björck-Pereyra error magnitude solver (BP-EMS) is presented to improve decoding efficiency and hardware complexity. The chip measurement results reveal that our proposed soft (32400, 32208) BCH decoder for DVB-S2 system can achieve 314.5 Mb/s with a gate-count of 26.9 K in standard 90 nm 1P9M CMOS technology. Extended for fully supporting 21 modes in the DVB-S2 system, our approach can achieve 300 MHz operation frequency with a gate-count of 32.4 K.

    Original languageEnglish
    Article number5607213
    Pages (from-to)2330-2340
    Number of pages11
    JournalIEEE Journal of Solid-State Circuits
    Volume45
    Issue number11
    DOIs
    StatePublished - 1 Nov 2010

    Keywords

    • Bose-Chaudhuri-Hochquenghem (BCH) codes
    • DVB-S2
    • digital video broadcasting
    • error-correction coding

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