A 2.5-V 14-bit 180-mW cascaded Σ△ ADC for ADSL2+ applications

Teng Hung Chang; Lan-Rong Dung; Jwin Yen Guo; Kai Jiun Yang

doi:10.1109/ASSCC.2006.357851

A 2.5-V 14-bit 180-mW cascaded Σ△ ADC for ADSL2+ applications

Teng Hung Chang^*, Lan-Rong Dung, Jwin Yen Guo, Kai Jiun Yang

^*Corresponding author for this work

Department of Electrical and Computer Engineering

Research output: Contribution to conference › Paper › peer-review

Abstract

This paper presents a sigma-delta (Σ △) analog-todigital converter (ADC) for the extended bandwidth asymmetric digital subscriber line application (ADSL2+). The core of the ADC is a cascaded 2-1-1 Σ△ modulator that employs a resonator-based topology in the first stage, three tri-level quantizers, and two different pairs of reference voltages. As shown in the experimental result, for a 2.2 MHz signal bandwidth, the ADC achieves a dynamic range of 86 dB and a peak signal-to-noise and distortion ratio (SNDR) of 78 dB with an oversampling ratio of 16. It is implemented in a 0.25-μm CMOS technology, in a 2.4mm² active area including decimation filter and reference voltage buffers, and dissipates 180 mW from a 2.5-V power supply.

Original language	English
Pages	59-62
Number of pages	4
DOIs	https://doi.org/10.1109/ASSCC.2006.357851
State	Published - 2006
Event	2006 IEEE Asian Solid-State Circuits Conference, ASSCC 2006 - Hangzhou, China Duration: 13 Nov 2006 → 15 Nov 2006

Conference

Conference	2006 IEEE Asian Solid-State Circuits Conference, ASSCC 2006
Country/Territory	China
City	Hangzhou
Period	13/11/06 → 15/11/06

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10.1109/ASSCC.2006.357851

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@conference{dc469ecf28d742a4815ecc6ffd074775,

title = "A 2.5-V 14-bit 180-mW cascaded Σ△ ADC for ADSL2+ applications",

abstract = "This paper presents a sigma-delta (Σ △) analog-todigital converter (ADC) for the extended bandwidth asymmetric digital subscriber line application (ADSL2+). The core of the ADC is a cascaded 2-1-1 Σ△ modulator that employs a resonator-based topology in the first stage, three tri-level quantizers, and two different pairs of reference voltages. As shown in the experimental result, for a 2.2 MHz signal bandwidth, the ADC achieves a dynamic range of 86 dB and a peak signal-to-noise and distortion ratio (SNDR) of 78 dB with an oversampling ratio of 16. It is implemented in a 0.25-μm CMOS technology, in a 2.4mm2 active area including decimation filter and reference voltage buffers, and dissipates 180 mW from a 2.5-V power supply.",

author = "Chang, {Teng Hung} and Lan-Rong Dung and Guo, {Jwin Yen} and Yang, {Kai Jiun}",

year = "2006",

doi = "10.1109/ASSCC.2006.357851",

language = "English",

pages = "59--62",

note = "2006 IEEE Asian Solid-State Circuits Conference, ASSCC 2006 ; Conference date: 13-11-2006 Through 15-11-2006",

}

TY - CONF

T1 - A 2.5-V 14-bit 180-mW cascaded Σ△ ADC for ADSL2+ applications

AU - Chang, Teng Hung

AU - Dung, Lan-Rong

AU - Guo, Jwin Yen

AU - Yang, Kai Jiun

PY - 2006

Y1 - 2006

N2 - This paper presents a sigma-delta (Σ △) analog-todigital converter (ADC) for the extended bandwidth asymmetric digital subscriber line application (ADSL2+). The core of the ADC is a cascaded 2-1-1 Σ△ modulator that employs a resonator-based topology in the first stage, three tri-level quantizers, and two different pairs of reference voltages. As shown in the experimental result, for a 2.2 MHz signal bandwidth, the ADC achieves a dynamic range of 86 dB and a peak signal-to-noise and distortion ratio (SNDR) of 78 dB with an oversampling ratio of 16. It is implemented in a 0.25-μm CMOS technology, in a 2.4mm2 active area including decimation filter and reference voltage buffers, and dissipates 180 mW from a 2.5-V power supply.

AB - This paper presents a sigma-delta (Σ △) analog-todigital converter (ADC) for the extended bandwidth asymmetric digital subscriber line application (ADSL2+). The core of the ADC is a cascaded 2-1-1 Σ△ modulator that employs a resonator-based topology in the first stage, three tri-level quantizers, and two different pairs of reference voltages. As shown in the experimental result, for a 2.2 MHz signal bandwidth, the ADC achieves a dynamic range of 86 dB and a peak signal-to-noise and distortion ratio (SNDR) of 78 dB with an oversampling ratio of 16. It is implemented in a 0.25-μm CMOS technology, in a 2.4mm2 active area including decimation filter and reference voltage buffers, and dissipates 180 mW from a 2.5-V power supply.

UR - http://www.scopus.com/inward/record.url?scp=34250805463&partnerID=8YFLogxK

U2 - 10.1109/ASSCC.2006.357851

DO - 10.1109/ASSCC.2006.357851

M3 - Paper

AN - SCOPUS:34250805463

SP - 59

EP - 62

T2 - 2006 IEEE Asian Solid-State Circuits Conference, ASSCC 2006

Y2 - 13 November 2006 through 15 November 2006

ER -

A 2.5-V 14-bit 180-mW cascaded Σ△ ADC for ADSL2+ applications

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