A 20-Gb/s optical receiver with integrated photo detector in 40-nm CMOS

Shih Hao Huang, Wei-Zen Chen

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

10 Scopus citations

Abstract

This paper presents a 20-Gb/s monolithically integrated CMOS optical receiver, integrating a photo detector, a transimpedance amplifier, and a post limiting amplifier on a single chip. Incorporating a 2-D meshed spatially-modulated light detector, the optical receiver achieves a record-high speed and is capable of delivering 80-dBΩ conversion gain when driving 50-Ω output loads. Nested-feedback topologies are adopted for transimpedance and post limiting amplifier design to achieve broad-band and high-gain operations without shunt-peaking inductors. Implemented in a generic 40-nm CMOS technology, the chip size is 0.6 × 0.54 mm2. This receiver core drains 30 mW from 1-V supply.

Original languageEnglish
Title of host publicationProceedings of the 2013 IEEE Asian Solid-State Circuits Conference, A-SSCC 2013
Pages225-228
Number of pages4
DOIs
StatePublished - 1 Dec 2013
Event2013 9th IEEE Asian Solid-State Circuits Conference, A-SSCC 2013 - Singapore, Singapore
Duration: 11 Nov 201313 Nov 2013

Publication series

NameProceedings of the 2013 IEEE Asian Solid-State Circuits Conference, A-SSCC 2013

Conference

Conference2013 9th IEEE Asian Solid-State Circuits Conference, A-SSCC 2013
Country/TerritorySingapore
CitySingapore
Period11/11/1313/11/13

Keywords

  • OEIC
  • Optical Receiver
  • Photo Detector (PD)
  • Transimpedance Amplifier (TIA)

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