TY - GEN
T1 - A 20-Gb/s, 2.4 pJ/bit, Fully Integrated Optical Receiver with a Baud-Rate Clock and Data Recovery
AU - Lee, Yuan Sheng
AU - Chen, Wei-Zen
N1 - Publisher Copyright:
© 2018 IEEE.
PY - 2018/4/26
Y1 - 2018/4/26
N2 - A single chip optical receiver comprising of a fontend amplifier, a CDR, and a 1:4 demultiplexer is presented. Incorporating with an integrating type receiver front-end, a baud-rate CDR is proposed to achieve both high sensitivity and highly energy-efficient operation. Besides, a hybrid loop filter consisting of analog decimation and digital post processing is proposed for high speed operation with low power consumption. By applying a PRBS 231-1 test pattern, the input sensitivity of the optical receiver is about -9.2 dBm for a BER of less than 10-12 (with a PD responsivity of 0.53 A/W). The recovered data jitter at the demultiplexer output is about 1.74 ps (rms). Implemented in a TSMC 40 nm CMOS process, the core area of the receiver chip is only 0.09 mm2. It demonstrates an energy efficiency of 2.4 pJ/bit for the entire receiver at 20 Gbps operation.
AB - A single chip optical receiver comprising of a fontend amplifier, a CDR, and a 1:4 demultiplexer is presented. Incorporating with an integrating type receiver front-end, a baud-rate CDR is proposed to achieve both high sensitivity and highly energy-efficient operation. Besides, a hybrid loop filter consisting of analog decimation and digital post processing is proposed for high speed operation with low power consumption. By applying a PRBS 231-1 test pattern, the input sensitivity of the optical receiver is about -9.2 dBm for a BER of less than 10-12 (with a PD responsivity of 0.53 A/W). The recovered data jitter at the demultiplexer output is about 1.74 ps (rms). Implemented in a TSMC 40 nm CMOS process, the core area of the receiver chip is only 0.09 mm2. It demonstrates an energy efficiency of 2.4 pJ/bit for the entire receiver at 20 Gbps operation.
KW - baud rate CDR
KW - demultiplexer
KW - optical receiver
UR - http://www.scopus.com/inward/record.url?scp=85057090554&partnerID=8YFLogxK
U2 - 10.1109/ISCAS.2018.8351036
DO - 10.1109/ISCAS.2018.8351036
M3 - Conference contribution
AN - SCOPUS:85057090554
T3 - Proceedings - IEEE International Symposium on Circuits and Systems
BT - 2018 IEEE International Symposium on Circuits and Systems, ISCAS 2018 - Proceedings
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 2018 IEEE International Symposium on Circuits and Systems, ISCAS 2018
Y2 - 27 May 2018 through 30 May 2018
ER -
